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參數(shù)資料
| 型號： | COP8SGR7-Q3 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| 中文描述： | 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內存，2個比較器和USART |
| 文件頁數(shù)： | 24/62頁 |
| 文件大?。?/td> | 913K |
| 代理商： | COP8SGR7-Q3 |
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6.0 Timers
(Continued)
6.3 TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
TxC3
Timer mode control
TxC2
Timer mode control
TxC1
Timer mode control
TxC0
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in Mode
3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxENA
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
TxPNDB Timer Interrupt Pending Flag
TxENB
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
The timer mode control bits (TxC3, TxC2 and TxC1) are
detailed below:
Mode
TxC3
TxC2
TxC1
Description
Interrupt A
Source
Autoreload RA
Autoreload RA
Interrupt B
Source
Autoreload RB
Autoreload RB
Timer
Counts On
t
C
1
1
1
0
0
1
0
PWM: TxA Toggle
PWM: No TxA
Toggle
External Event
Counter
External Event
Counter
Captures:
TxA Pos. Edge
TxB Pos. Edge
Captures:
TxA Pos. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
t
C
2
0
0
0
Timer Underflow
Pos. TxB Edge
Pos. TxA
Edge
Pos. TxA
Edge
t
C
0
0
1
Timer Underflow
Pos. TxB Edge
3
0
1
0
Pos. TxA Edge
or Timer
Underflow
Pos. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Pos. TxB Edge
1
1
0
Neg. TxB
Edge
t
C
0
1
1
Neg. TxB
Edge
t
C
1
1
1
Neg. TxB
Edge
t
C
C
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