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      參數(shù)資料
      型號: COP8SGH840N3
      廠商: National Semiconductor Corporation
      英文描述: 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
      中文描述: 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內存,2個比較器和USART
      文件頁數(shù): 26/62頁
      文件大小: 913K
      代理商: COP8SGH840N3
      7.0 Power Saving Features
      (Continued)
      7.2 IDLE MODE
      The device is placed in the IDLE mode by writing a “1” to the
      IDLE flag (G6 data bit). In this mode, all activities, except the
      associated on-board oscillator circuitry and the IDLE Timer
      T0, are stopped.
      As with the HALT mode, the device can be returned to
      normal operation with a reset, or with a Multi-Input Wakeup
      from the L Port. Alternately, the microcontroller resumes
      normal operation from the IDLE mode when the twelfth bit
      (representing 4.096 ms at internal clock frequency of
      10 MHz, t
      C
      = 1 μs) of the IDLE Timer toggles.
      This toggle condition of the twelfth bit of the IDLE Timer T0 is
      latched into the T0PND pending flag.
      The user has the option of being interrupted with a transition
      on the twelfth bit of the IDLE Timer T0. The interrupt can be
      enabled or disabled via the T0EN control bit. Setting the
      T0EN flag enables the interrupt and vice versa.
      The user can enter the IDLE mode with the Timer T0 inter-
      rupt enabled. In this case, when the T0PND bit gets set, the
      device will first execute the Timer T0 interrupt service routine
      and then return to the instruction following the “Enter Idle
      Mode” instruction.
      Alternatively, the user can enter the IDLE mode with the
      IDLE Timer T0 interrupt disabled. In this case, the device will
      resume normal operation with the instruction immediately
      following the “Enter IDLE Mode” instruction.
      Note:
      It is necessary to program two NOP instructions following both the set
      HALT mode and set IDLE mode instructions. These NOP instructions
      are necessary to allow clock resynchronization following the HALT or
      IDLE modes.
      10131725
      FIGURE 18. Wakeup from HALT
      10131726
      FIGURE 19. Wakeup from IDLE
      C
      www.national.com
      26
      相關PDF資料
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      COP8SGA840N6 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
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