9.0 Interrupts (Continued) 9.3.1 VIS Execution When the VIS instruction is executed it activates the arb" />
參數(shù)資料
型號(hào)： COP8SAC744J3
廠商： National Semiconductor
文件頁(yè)數(shù)： 25/62頁(yè)
文件大?。?/td> 0K
描述： IC MCU EPROM 8 BIT 4K 44-PLCC
標(biāo)準(zhǔn)包裝： 80
系列： COP8™ 8SA
核心處理器： COP8
芯體尺寸： 8-位
速度： 10MHz
連通性： Microwire/Plus（SPI）
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 4KB（4K x 8）
程序存儲(chǔ)器類型： EPROM，UV
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 托盤
其它名稱： *COP8SAC744J3
COP8SAC744J3B
9.0 Interrupts (Continued)
9.3.1 VIS Execution
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If the only active
interrupt is software trap, than E0 is generated. This number
replaces the lower byte of the PC. The upper byte of the PC
remains unchanged. The new PC is therefore pointing to the
vector of the active interrupt with the highest arbitration
ranking. This vector is read from program memory and
placed into the PC which is now pointed to the 1st instruction
of the service routine of the active interrupt with the highest
arbitration ranking.
Figure 22 illustrates the different steps performed by the VIS
instruction.
Figure 23 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
DS012838-29
FIGURE 22. VIS Operation
COP8SA
Family
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