參數(shù)資料
型號(hào)： COP8SAC728Q3
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging
中文描述： 8-BIT, UVPROM, 10 MHz, MICROCONTROLLER, CDIP28
封裝： HERMETIC SEALED, WINDOWED, DIP-28
文件頁(yè)數(shù)： 11/60頁(yè)
文件大?。?/td> 787K
代理商： COP8SAC728Q3
AC Electrical Characteristics
(Continued)
40C
≤
T
A
≤
+85C unless otherwise specified.
Parameter
Inputs
t
SETUP
Conditions
Min
Typ
Max
Units
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
R
L
= 2.2k, C
L
= 100 pF
200
500
60
150
ns
ns
ns
ns
t
HOLD
Output Propagation Delay (Note 16)
t
PD1
, t
PD0
SO, SK
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
0.7
1.75
1.0
2.5
μs
μs
μs
μs
ns
ns
ns
All Others
MICROWIRE Setup Time (t
UWS
) (Note 16)
MICROWIRE Hold Time (t
UWH
) (Note 16)
MICROWIRE Output Propagation Delay (t
UPD
)
MICROWIRE Maximum Shift Clock
Master Mode
Slave Mode
Input Pulse Width (Note 17)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Reset Pulse Width
20
56
220
500
1
kHz
MHz
1
1
1
1
1
t
C
t
C
t
C
t
C
μs
Note 11:
t
C
= Instruction cycle time (Clock input frequency divided by 10).
Note 12:
Maximum rate of voltage change must be
<
0.5 V/ms.
Note 13:
Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180 out of phase with CKI, inputs connected to V
CC
and outputs driven low but not connected to a load.
Note 14:
The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of I
HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 pro-
grammed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
CC
; clock monitor disabled. Parameter refers
to HALT mode entered via setting bit 7 of the G Port data register.
Note 15:
Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
>
V
CC
and the pins will have sink current to V
CC
when
biased at voltages
V
(the pins do not have source current when biased at a voltage below V
). The effective resistance to V
is 750
(typical). These two
pins will not latch up. The voltage at the pins must be limited to
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes
ESD transients.
Note 16:
The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 17:
Parameter characterized but not tested.
Note 18:
Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.
DS012838-9
FIGURE 4. MICROWIRE/PLUS Timing
www.national.com
11
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