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| 型號： | COP8SAB7SLB9 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
| 中文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, QCC28 |
| 封裝： | CSP-28 |
| 文件頁數(shù)： | 40/60頁 |
| 文件大小： | 787K |
| 代理商： | COP8SAB7SLB9 |
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13.0 Instruction Set
13.1 INTRODUCTION
This section defines the instruction set of the COP8SAx
Family members. It contains information about the instruc-
tion set features, addressing modes and types.
13.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the follow-
ing features:
Mostly single-byte opcode instructions minimize pro-
gram size.
One instruction cycle for the majority of single-byte in-
structions to minimize program execution time.
Many single-byte, multiple function instructions such
as DRSZ.
Three memory mapped pointers: two for register indi-
rect addressing, and one for the software stack.
Sixteen memory mapped registers that allow an opti-
mized implementation of certain instructions.
Ability to set, reset, and test any individual bit in data
memory
address
memory-mapped I/O ports and registers.
Register-Indirect LOAD and EXCHANGE instructions
with optional automatic post-incrementing or decre-
menting of the register pointer. This allows for greater
efficiency (both in cycle time and program code) in
loading, walking across and processing fields in data
memory.
Unique instructions to optimize program size and
throughput efficiency. Some of these instructions are
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
space,
including
the
12.3 ADDRESSING MODES
The instruction set offers a variety of methods for specify-
ing memory addresses. Each method is called an ad-
dressing mode. These modes are classified into two cat-
egories:
operand
addressing
transfer-of-control addressing modes. Operand address-
ing modes are the various methods of specifying an ad-
dress
for
accessing
(reading
Transfer-of-control addressing modes are used in con-
junction with jump instructions to control the execution se-
quence of the software program.
modes
and
or
writing)
data.
13.3.1 Operand Addressing Modes
The operand of an instruction specifies what memory lo-
cation is to be affected by that instruction. Several differ-
ent operand addressing modes are available, allowing
memory locations to be specified in a variety of ways. An
instruction can specify an address directly by supplying
the specific address, or indirectly by specifying a register
pointer. The contents of the register (or in some cases,
two registers) point to the desired memory location. In the
immediate mode, the data byte to be used is contained in
the instruction itself.
Each addressing mode has its own advantages and dis-
advantages with respect to flexibility, execution speed,
and program compactness. Not all modes are available
with all instructions. The Load (LD) instruction offers the
largest number of addressing modes.
The available addressing modes are:
Direct
Register B or X Indirect
Register B or X Indirect with Post-Incrementing/
Decrementing
Immediate
Immediate Short
Indirect from Program Memory
The addressing modes are described below. Each de-
scription includes an example of an assembly language
instruction using the described addressing mode.
Direct.
The memory address is specified directly as a byte
in the instruction. In assembly language, the direct ad-
dress is written as a numerical value (or a label that has
been defined elsewhere in the program as a numerical
value).
Example: Load Accumulator Memory Direct
LD A,05
Reg/Data
Memory
Accumulator
Memory Location
0005 Hex
Contents
Before
XX Hex
A6 Hex
Contents
After
A6 Hex
A6 Hex
Register B or X Indirect.
The memory address is specified
by the contents of the B Register or X register (pointer regis-
ter). In assembly language, the notation [B] or [X] specifies
which register serves as the pointer.
Example: Exchange Memory with Accumulator, B Indirect
X A,[B]
Reg/Data
Memory
Accumulator
Memory Location
0005 Hex
B Pointer
or
X
Contents
Before
01 Hex
87 Hex
Contents
After
87 Hex
01 Hex
05 Hex
with
05 Hex
Register
Decrementing.
The relevant memory address is specified
by the contents of the B Register or X register (pointer regis-
ter). The pointer register is automatically incremented or
decremented after execution, allowing easy manipulation of
memory blocks with software loops. In assembly language,
the notation [B+], [B], [X+], or [X] specifies which register
serves as the pointer, and whether the pointer is to be incre-
mented or decremented.
Example: Exchange Memory with Accumulator, B Indirect
with Post-Increment
X A,[B+]
B
Indirect
Post-Incrementing/
Reg/Data
Memory
Accumulator
Memory Location
0005 Hex
B Pointer
Contents
Before
03 Hex
62 Hex
Contents
After
62 Hex
03 Hex
05 Hex
06 Hex
Intermediate.
The data for the operation follows the instruc-
tion opcode in program memory. In assembly language, the
number sign character (
#
) indicates an immediate operand.
www.national.com
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| COP8SAC5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
| COP8SAC7 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
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