- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗3794 > COP8SAA716N8 (National Semiconductor)IC MCU OTP 8BIT 1K 16-DIP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | COP8SAA716N8 |
| 寤犲晢锛� | National Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 9/62闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 8BIT 1K 16-DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 25 |
| 绯诲垪锛� | COP8™ 8SA |
| 鏍稿績铏曠悊鍣細 | COP8 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 10MHz |
| 閫ｉ€氭€э細 | Microwire/Plus锛圫PI锛� |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 12 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 1KB锛�1K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 64 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 16-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
| 鍏跺畠鍚嶇ū锛� | *COP8SAA716N8 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�鐣�(d膩ng)鍓嶇9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�
6.0 Functional Description (Continued)
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumu-
lator (A) bits can also be directly and individually tested.
RAM contents are undefined upon power-up.
TABLE 1. Program/Data Memory Sizes
Program
Data
User
Device
Memory
Storage
(Bytes)
COP8SAA7
1024
64
8
COP8SAB7
2048
128
8
COP8SAC7
4096
128
8
6.4 ECON (CONFIGURATION) REGISTER
The ECON register is used to configure the user selectable
clock, security, power-on reset, WATCHDOG, and HALT
options. The register can be programmed and read only in
EPROM programming mode. Therefore, the register should
be programmed at the same time as the program memory.
The contents of the ECON register shipped from the factory
read 00 Hex (windowed device), 80 Hex (OTP device) or as
specified by the customer (ROM device).
The format of the ECON register is as follows:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
POR
SECURITY
CKI 2
CKI 1
WATCH
Reserved
HALT
DOG
Bit 7
= x
This is for factory test. The polarity is al-
ways 0.
Bit 6
= 1
Power-on reset enabled.
= 0
Power-on reset disabled.
Bit 5
= 1
Security enabled. EPROM read and write
are not allowed.
= 0
Security disabled. EPROM read and write
are allowed.
Bits 4, 3 = 0, 0 External CKI option selected. G7 is avail-
able as a HALT restart and/or general pur-
pose input. CKI is clock input.
= 0, 1 R/C oscillator option selected. G7 is avail-
able as a HALT restart and/or general pur-
pose input. CKI clock input. Internal R/C
components are supplied for maximum
R/C frequency.
= 1, 0 Crystal oscillator with on-chip crystal bias
resistor disabled. G7 (CKO) is the clock
generator output to crystal/resonator.
= 1, 1 Crystal oscillator with on-chip crystal bias
resistor enabled. G7 (CKO) is the clock
generator output to crystal/resonator.
Bit 2
= 1
WATCHDOG feature disabled. G1 is a
general purpose I/O.
= 0
WATCHDOG feature enabled. G1 pin is
WATCHDOG output with waek pullup.
Bit 1
=
Reserved.
Bit 0
= 1
HALT mode disabled.
= 0
HALT mode enabled.
6.5 USER STORAGE SPACE IN EPROM
In addition to the ECON register, there are 8 bytes of
EPROM available for 鈥渦ser information鈥�. ECON and these 8
bytes are outside of the code area and are not protected by
the security bit of the ECON register. Even when security is
set, information in the 8-byte USER area is both read and
write enabled allowing the user to read from and write into
the area at all times while still protecting the code from
unauthorized access.
Both ECON and USER area, 9 bytes total, are outside of the
normal address range of the EPROM and can not be ac-
cessed by the executing software. This allows for the stor-
age of non-secured information. Typical uses are for storage
of serial numbers, data codes, version numbers, copyright
information, lot numbers, etc.
The COP8 assembler defines a special ROM section type,
CONF, into which the ECON and USER data may be coded.
Both ECON and User Data are programmed automatically
by programmers that are certified by National.
The following examples illustrate the declaration of ECON
and the User information.
Syntax:
[label:] .sect econ, conf
.db
value
;1 byte,
;configures options
.db
.endsect<user information>
;up to 8 bytes
Example: The following sets a value in the ECON register
and User Identification for a COP8SAC728M7. The ECON
bit values shown select options: Power-on enabled, Security
disabled, Crystal oscillator with on-chip bias disabled,
WATCHDOG enabled and HALT mode enabled.
.chip 8SAC
.sect econ, conf
.db
0x55
;por, extal, wd, halt
.db
'my v1.00'
;user data declaration
.endsect
...
.end start
Note: All programmers certified for programming this family of parts will
support programming of the CONFiguration section. Please contact
National or your device programmer supplier for more information.
6.6 OTP SECURITY
The device has a security feature that, when enabled, pre-
vents external reading of the OTP program memory. The
security bit in the ECON register determines, whether secu-
rity is enabled or disabled. If the security feature is disabled,
the contents of the internal EPROM may be read.
If the security feature is enabled, then any attempt to
externally read the contents of the EPROM will result in
the value FF Hex being read from all program locations.
Under no circumstances can a secured part be read. In
addition, with the security feature enabled, the write opera-
tion to the EPROM program memory and ECON register is
inhibited. The ECON register is readable regardless of the
state of the security bit. The security bit, when set, cannot
be erased, even in windowed packages. If the security bit
is set in a device in a windowed package, that device may be
erased but will not be further programmable.
If security is being used, it is recommended that all other bits
in the ECON register be programmed first. Then the security
bit can be programmed.
COP8SA
Family
www.national.com
16
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| COP8CDR9LVA8 | IC MCU CMOS 8BIT 68-PLCC |
| MC68HC705JJ7CDW | IC MCU 8BIT 20-SOIC |
| C8051F583-IQ | IC 8051 MCU 128K FLASH 32-QFP |
| 67068-0000 | CONN USB RT ANG RECPT TYPE B BLK |
| P89LPC952FBD,157 | IC 80C51 MCU FLASH 8K 44-LQFD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| COP8SAA716N8 | 鍒堕€犲晢:Texas Instruments 鍔熻兘鎻忚堪:IC 8BIT MCU OTP 1K 8SAA716 DIP16 |
| COP8SAA716N9 | 鍔熻兘鎻忚堪:IC MCU OTP 8BIT 1K 16DIP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:COP8™ 8SA 鍏跺畠鏈夐棞(gu膩n)鏂囦欢:STM32F101T8 View All Specifications 鐗硅壊鐢�(ch菐n)鍝�:STM32 32-bit Cortex MCUs 妯�(bi膩o)婧�(zh菙n)鍖呰:490 绯诲垪:STM32 F1 鏍稿績铏曠悊鍣�:ARM? Cortex?-M3 鑺珨灏哄:32-浣� 閫熷害:36MHz 閫ｉ€氭€�:I²C锛孖rDA锛孡IN锛孲PI锛孶ART/USART 澶栧湇瑷�(sh猫)鍌�:DMA锛孭DR锛孭OR锛孭VD锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):26 绋嬪簭瀛樺劜鍣ㄥ閲�:64KB锛�64K x 8锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:10K x 8 闆诲 - 闆绘簮 (Vcc/Vdd):2 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 10x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:36-VFQFN锛�36-VFQFPN 鍖呰:鎵樼洡 閰嶇敤:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2鏇村... 鍏跺畠鍚嶇ū:497-9032STM32F101T8U6-ND |
| COP8SAA720M7 | 鍔熻兘鎻忚堪:IC MCU OTP 8BIT 1K POR 20-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:COP8™ 8SA 鍏跺畠鏈夐棞(gu膩n)鏂囦欢:STM32F101T8 View All Specifications 鐗硅壊鐢�(ch菐n)鍝�:STM32 32-bit Cortex MCUs 妯�(bi膩o)婧�(zh菙n)鍖呰:490 绯诲垪:STM32 F1 鏍稿績铏曠悊鍣�:ARM? Cortex?-M3 鑺珨灏哄:32-浣� 閫熷害:36MHz 閫ｉ€氭€�:I²C锛孖rDA锛孡IN锛孲PI锛孶ART/USART 澶栧湇瑷�(sh猫)鍌�:DMA锛孭DR锛孭OR锛孭VD锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):26 绋嬪簭瀛樺劜鍣ㄥ閲�:64KB锛�64K x 8锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:10K x 8 闆诲 - 闆绘簮 (Vcc/Vdd):2 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 10x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:36-VFQFN锛�36-VFQFPN 鍖呰:鎵樼洡 閰嶇敤:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2鏇村... 鍏跺畠鍚嶇ū:497-9032STM32F101T8U6-ND |
| COP8SAA720M8 | 鍔熻兘鎻忚堪:IC MCU OTP 8BIT 1K POR 20-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:COP8™ 8SA 鍏跺畠鏈夐棞(gu膩n)鏂囦欢:STM32F101T8 View All Specifications 鐗硅壊鐢�(ch菐n)鍝�:STM32 32-bit Cortex MCUs 妯�(bi膩o)婧�(zh菙n)鍖呰:490 绯诲垪:STM32 F1 鏍稿績铏曠悊鍣�:ARM? Cortex?-M3 鑺珨灏哄:32-浣� 閫熷害:36MHz 閫ｉ€氭€�:I²C锛孖rDA锛孡IN锛孲PI锛孶ART/USART 澶栧湇瑷�(sh猫)鍌�:DMA锛孭DR锛孭OR锛孭VD锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):26 绋嬪簭瀛樺劜鍣ㄥ閲�:64KB锛�64K x 8锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:10K x 8 闆诲 - 闆绘簮 (Vcc/Vdd):2 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 10x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:36-VFQFN锛�36-VFQFPN 鍖呰:鎵樼洡 閰嶇敤:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2鏇村... 鍏跺畠鍚嶇ū:497-9032STM32F101T8U6-ND |
| COP8SAA720M9 | 鍔熻兘鎻忚堪:IC MCU OTP 8BIT 1K 20SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:COP8™ 8SA 鍏跺畠鏈夐棞(gu膩n)鏂囦欢:STM32F101T8 View All Specifications 鐗硅壊鐢�(ch菐n)鍝�:STM32 32-bit Cortex MCUs 妯�(bi膩o)婧�(zh菙n)鍖呰:490 绯诲垪:STM32 F1 鏍稿績铏曠悊鍣�:ARM? Cortex?-M3 鑺珨灏哄:32-浣� 閫熷害:36MHz 閫ｉ€氭€�:I²C锛孖rDA锛孡IN锛孲PI锛孶ART/USART 澶栧湇瑷�(sh猫)鍌�:DMA锛孭DR锛孭OR锛孭VD锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):26 绋嬪簭瀛樺劜鍣ㄥ閲�:64KB锛�64K x 8锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:10K x 8 闆诲 - 闆绘簮 (Vcc/Vdd):2 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 10x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:36-VFQFN锛�36-VFQFPN 鍖呰:鎵樼洡 閰嶇敤:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2鏇村... 鍏跺畠鍚嶇ū:497-9032STM32F101T8U6-ND |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
