- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗1908 > COP8SAA716M8/NOPB (National Semiconductor)IC MCU OTP 8BIT 1K 16-SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | COP8SAA716M8/NOPB |
| 寤犲晢锛� | National Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/62闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 8BIT 1K 16-SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 绯诲垪锛� | COP8™ 8SA |
| 鏍稿績铏曠悊鍣細 | COP8 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 10MHz |
| 閫ｉ€氭€э細 | Microwire/Plus锛圫PI锛� |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 12 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 1KB锛�1K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 64 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1281 (CN2011-ZH PDF) |
| 鍏跺畠鍚嶇ū锛� | *COP8SAA716M8 *COP8SAA716M8/NOPB COP8SAA716M8 |
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6.0 Functional Description (Continued)
6.7 RESET
The device is initialized when the RESET pin is pulled low or
the On-chip Power-On Reset is enabled.
The following occurs upon initialization:
Port L: TRISTATE
Port C: TRISTATE
Port G: TRISTATE
Port F: TRISTATE
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR: UNAFFECTED after RESET with power already
applied
RANDOM after RESET at power-on
T1CNTRL: CLEARED
Accumulator, Timer 1:
RANDOM after RESET with crystal clock option
(power already applied)
UNAFFECTED after RESET with R/C clock option
(power already applied)
RANDOM after RESET at power-on
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
Initialized to RAM address 02F Hex (devices with
64 bytes of RAM), or initialized to
RAM address 06F Hex (devices with
128 bytes of RAM).
B and X Pointers:
UNAFFECTED after RESET with power
already applied
RANDOM after RESET at power-on
RAM:
UNAFFECTED after RESET with power already
applied
RANDOM after RESET at power-on
WATCHDOG (if enabled):
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are
inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
C clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
C鈥�32 tC clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will go high.
6.7.1 External Reset
The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
tion cycle to guarantee a valid reset. During Power-Up ini-
tialization, the user must ensure that the RESET pin is held
low until the device is within the specified V
CC voltage. An
R/C circuit on the RESET pin with a delay 5 times (5x)
greater than the power supply rise time or 15 s whichever is
greater, is recommended. Reset should also be wide enough
to ensure crystal start-up upon Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
A recommended reset circuit for this deviced is shown in
Figure 9.
6.7.2 On-Chip Power-On Reset
The on-chip reset circuit is selected by a bit in the ECON
register. When enabled, the device generates an internal
reset as V
CC rises to a voltage level above 2.0V. The on-chip
reset circuitry is able to detect both fast and slow rise times
on V
CC (VCC rise time between 10 ns and 50 ms).
Under no circumstances should the RESET pin be allowed
to float. If the on-chip Power-On Reset feature is being used,
RESET pin should be connected directly to V
CC. The output
of the power-on reset detector will always preset the Idle
timer to 0FFF(4096 t
C). At this time, the internal reset will be
generated.
If the Power-On Reset feature is enabled, the internal reset
will not be turned off until the Idle timer underflows. The
internal reset will perform the same functions as external
reset. The user is responsible for ensuring that V
CC is at the
minimum level for the operating frequency within the 4096
t
C. After the underflow, the logic is designed such that no
additional internal resets occur as long as V
CC remains
above 2.0V.
Note: While the POR feature of the COP8SAx was never intended to function
as a brownout detector, there are certain constraints of this block that
the system designer must address to properly recover from a brownout
condition. This is true regardless of whether the internal POR or the
external reset feature is used.
A brownout condition is reached when VCC of the device goes below
the minimum operating conditions of the device. The minimum guar-
anteed operating conditions are defined as VCC = 4.5V @ 10 MHz CKI,
VCC = 2.7V @ 4 MHz, or VCC = 2.0V during HALT mode (or when CKI
is stopped) operation.
When using either the external reset or the POR feature to recover
from a brownout condition, VCC must be lowered to 0.25V or an
external reset must be applied whenever it goes below the minimum
operating conditions as stated above.
DS012838-13
FIGURE 8. Reset Logic
DS012838-14
RC >5x power supply rise time or 15 s, whichever is greater.
FIGURE 9. Reset Circuit Using External Reset
COP8SA
Family
www.national.com
17
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| COP8SAA716N8 | 鍒堕€犲晢:Texas Instruments 鍔熻兘鎻忚堪:IC 8BIT MCU OTP 1K 8SAA716 DIP16 |
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