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| 型號： | COP8SA |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based and One-Time Programmable (OTP) Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging(8位基于CMOS ROM和一次可編程的帶1K到4K存儲器，加電復(fù)位和極小封裝的微控制器) |
| 中文描述： | 8位的CMOS基于ROM和一次性可編程（OTP）的經(jīng)銷商到4K內(nèi)存，上電復(fù)位微控制器，以及超小型封裝（8位基于的CMOS光盤和一次可編程的帶一千到4K的存儲器，加電復(fù)位和極小封裝的微控制器） |
| 文件頁數(shù)： | 37/60頁 |
| 文件大?。?/td> | 776K |
| 代理商： | COP8SA |
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11.0 MICROWIRE/PLUS
(Continued)
11.1.2 MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration
register. Table 10 summarizes the settings required to enter
the Slave mode of operation.
This table assumes that the control flag MSEL is set.
TABLE 10. MICROWIRE/PLUS Mode Settings
G4 (SO)
G5 (SK)
G4
G5
Operation
Config. Bit
Config. Bit
Fun.
Fun.
1
1
SO
Int.
MICROWIRE/PLUS
SK
Master
0
1
TRI-
Int.
MICROWIRE/PLUS
STATE
SK
Master
1
0
SO
Ext.
MICROWIRE/PLUS
SK
Slave
0
0
TRI-
Ext.
MICROWIRE/PLUS
STATE
SK
Slave
The user must set the BUSY flag immediately upon entering
the Slave mode. This ensures that all data bits sent by the
Master is shifted properly. After eight clock pulses the BUSY
flag is clear, the shift clock is stopped, and the sequence
may be repeated.
10.1.3 Alternate SK Phase Operation
and SK Idle Polarity
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK idle polarity can be either high or low.
The polarity is selected by bit 5 of Port G data register. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted
in on the falling edge of the SK clock and shifted out on the
rising edge of the SK clock. Bit 6 of Port G configuration
register selects the SK edge.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configu-
ration bit. The SKSEL flag will power up in the reset condi-
tion, selecting the normal SK signal.
TABLE 11. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
Port G
SO Clocked Out On:
SI Sampled On:
SK Idle
Phase
SK Phase
G6 (SKSEL)
Config. Bit
0
1
0
1
G5
Data Bit
0
0
1
1
Normal
Alternate
Alternate
Normal
SK Falling Edge
SK Rising Edge
SK Rising Edge
SK Falling Edge
SK Rising Edge
SK Falling Edge
SK Falling Edge
SK Rising Edge
Low
Low
High
High
DS012838-33
FIGURE 25. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
DS012838-34
FIGURE 26. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low
C
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| COP8SA_00 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and One-Time Programmable (OTP) Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
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| COP8SAA7 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
| COP8SAA716M7 | 功能描述:IC MCU OTP 8BIT 1K POR 16-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:COP8™ 8SA 標準包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
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