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參數(shù)資料
| 型號： | CMQ82C55AZ96 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Programmable Peripheral Interface |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, PQFP44 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-022AB, MQFP-44 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 502K |
| 代理商： | CMQ82C55AZ96 |
3
FN6140.1
June 28, 2005
Functional Diagram
Functional Description
Data Bus Buffer
This three-state bidirectional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status
information are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
(CS)
Chip Select. A “l(fā)ow” on this input pin enables the
communication between the 82C55A and the CPU.
(RD)
Read. A “l(fā)ow” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
(WR)
Write. A “l(fā)ow” on this input pin enables the CPU to
write data or control words into the 82C55A.
(A0 and A1)
Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).
(RESET)
Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode.
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
GROUP B
CONTROL
GROUP A
CONTROL
DATA BUS
BUFFER
READ
WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7-D0
POWER
SUPPLIES
+5V
GND
BIDIRECTIONAL
DATA BUS
I/O
PA7-PA0
I/O
PC7-PC4
I/O
PC3-PC0
I/O
PB7-PB0
8-BIT
INTERNAL
DATA BUS
FIGURE 1. FUNCTIONAL DIAGRAM
82C55A BASIC OPERATION
A1
A0
RD
WR
CS
INPUT OPERATION
(READ)
0
0
0
1
0
Port A
→
Data Bus
0
1
0
1
0
Port B
→
Data Bus
1
0
0
1
0
Port C
→
Data Bus
1
1
0
1
0
Control Word
→
Data Bus
OUTPUT OPERATION
(WRITE)
0
0
1
0
0
Data Bus
→
Port A
0
1
1
0
0
Data Bus
→
Port B
1
0
1
0
0
Data Bus
→
Port C
1
1
1
0
0
Data Bus
→
Control
DISABLE FUNCTION
X
X
X
X
1
Data Bus
→
Three-State
X
X
1
1
0
Data Bus
→
Three-State
MS82C55A, MQ82C55A
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