參數(shù)資料
型號(hào): CMPWR100S
英文描述: Analog IC
中文描述: 模擬IC
文件頁(yè)數(shù): 8/10頁(yè)
文件大?。?/td> 119K
代理商: CMPWR100S
2000 California Micro Devices Corp. All rights reserved.
8
10/20/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CMPWR100
CALIFORNIA MICRO DEVICES
Typical Transient Characteristics cont
d
V
Power down (V
= 0V).
This shows the output
response of the regulator during a complete power down
situation under full load conditions.
Full priority is assigned to the regulator since V
is not
present. The regulator remains enabled throughout the
power down sequence.
The output remains in full regulation until V
collapses
below 4 volts. This demonstrates the low dropout
characteristics of the regulator.
Load Step response.
This shows the output response
of the regulator during a step load change from 5mA to
200mA.
During the application and removal of the step load,
minimal overshoot is observed and the transient has
settled with 10μs.
V
OUT
offset = 3.3V
Line Step Response.
This shows the regulator output
response to a step transient (1Vpp) applied to the V
CC
line voltage.
The output experiences a peak disturbance of 80mV
during the line transient.
V
OUT
offset = 3.3V, V
CC
offset = 5.0V
3.02V
Drive
200mA Load
V
CC
V
OUT
M 5.00ms
1.00V
5.00V
Ch2
3
2
Ch3
1.00V
10.0kS/s
Tek
1 Acqs
Ch1
1.72V
5mA to 200mA Load Step
V
OUT
M 10.0μs
100mV
Ch2
3
2
2.00V
5.00MS/s
Tek
2 Acqs
Ch2
4.92V
4.5V tp 5.5V
V
OUT
V
CC
5mA Load
M 100μs
100mV
Ch2
2
1.00V
500kS/s
Tek
2 Acqs
Ch2
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