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| 型號： | CM8872CSI |
| 英文描述： | DTMF Receiver |
| 中文描述： | 雙音多頻接收器 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 76K |
| 代理商： | CM8872CSI |
200
1
California Micro Devices Corp. All rights reserved.
1
2
/
18
/2001
5
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
CM8870/70C
CALIFORNIA MICRO DEVICES
Functional Description
The CAMD CM8870/70C DTMF Integrated Receiver
provides the design engineer with not only low power
consumption, but high performance in a small 18-pin
DIP, SOIC, or 20-pin PLCC package configuration. The
CM8870/70C
’
s internal architecture consists of a
band-split filter section which separates the high and low
tones of the received pair, followed by a digital decode
(counting) section which verifies both the frequency and
duration of the received tones before passing the
resultant 4-bit code to the output bus.
Filter Section
Separation of the low-group and high-group tones is
achieved by applying the dual-tone signal to the inputs of
two 9
th
-order switched capacitor bandpass filters. The
bandwidths of these filters correspond to the bands
enclosing the low-group and high-group tones (See
Figure 3). The filter section also incorporates notches at
350Hz and 440Hz which provides excellent dial tone
rejection. Each filter output is followed by a single order
switched capacitor section which smooths the signals
prior to limiting. Signal limiting is performed by high-gain
comparators. These comparators are provided with a
hysteresis to prevent detection of unwanted low-level
signals and noise. The outputs of the comparators
provide full-rail logic swings at the frequencies of the
incoming tones.
Decoder Section
The CM8870/70C decoder uses a digital counting
technique to determine the frequencies of the limited
tones and to verify that these tones correspond to
standard DTMF frequencies. A complex averaging
algorithm is used to protect against tone simulation by
extraneous signals (such as voice) while providing
tolerance to small frequency variations. The averaging
algorithm has been developed to ensure an optimum
combination of immunity to
“
talk-off
”
and tolerance to the
presence of interfering signals (third tones) and noise.
When the detector recognizes the simultaneous pres-
ence of two valid tones (known as
“
signal condition
”
), it
raises the
“
Early Steering
”
flag (ESt). Any subsequent
loss of signal condition will cause ESt to fall.
Steering Circuit
Before the registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to as
“
character-recognition-condition
”
). This check is per-
formed by an external RC time constant driven by E
. A
logic high on ESt causes V
(See Figure 4) to rise as the
capacitor discharges. Providing signal condition is
maintained (ESt remains high) for the validation period
(t
), V
reaches the threshold (V
) of the steering logic
to register the tone pair, thus latching its corresponding
4-bit code (See Figure 2) into the output latch. At this
point, the GT output is activated and drives VC to V
.
GT continues to drive high as long as ESt remains high,
signaling that a received tone pair has been registered.
The contents of the output latch are made available on
the 4-bit output bus by raising the three-state control
input (TOE) to a logic high. The steering circuit works in
reverse to validate the interdigit pause between signals.
Thus, as well as rejecting signals too short to be consid-
ered valid, the receiver will tolerate signal interruptions
(drop outs) too short to be considered a valid pause.
This capability together with the capability of selecting
the steering time constants externally, allows the de-
signer to tailor performance to meet a wide variety of
system requirements.
Guard Time Adjustment
In situations which do not require independent selection
of receive and pause, the simple steering circuit of
Figure 4 is applicable. Component values are chosen
according to the following formula:
t
REC
= t
DP
+ t
GTP
t
GTP
= 0.67 RC
The value of t
is a parameter of the device and t
is
the minimum signal duration to be recognized by the
receiver. A value for C of 0.1μF is recommended for
most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a t
of
40ms would be 300K. A typical circuit using this steering
configuration is shown in Figure 1. The timing require-
ments for most telecommunication applications are
satisfied with this circuit. Different steering arrange-
ments may be used to select independently the
guard-times for tone-present (t
) and tone absent (t
GTA
).
This may be necessary to meet system specifications
which place both accept and reject limits on both tone
duration and interdigit pause.
Guard time adjustment also allows the designer to tailor
system parameters such as talk-off and noise immunity.
Increasing t
improves talk-off performance, since it
reduces the probability that tones simulated by speech
will maintain signal condition for long enough to be
registered. On the other hand, a relatively short t
REC
with
a long t
would be appropriate for extremely noisy
environments where fast acquisition time and immunity
to drop-outs would be requirements. Design information
for guard time adjustment is shown in Figure 5.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CM8880 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:CMOS Integrated DTMF Transceiver |
| CM8880-1 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:CMOS Integrated DTMF Transceiver |
| CM8880-1CI | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:CMOS Integrated DTMF Transceiver |
| CM8880-1DI | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:CMOS Integrated DTMF Transceiver |
| CM8880-1EI | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:CMOS Integrated DTMF Transceiver |
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