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2006 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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Fax: 408.263.7846
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www.cmd.com 03/20/06
CM3702
Product Description (cont’d)
Two enable inputs provide flexibility in powering down
the device. For maximum power saving in shutdown,
both the charge pump and LDO regulator should be
disabled. For applications that require the 5V output to
be re-established with minimum delay after shutdown,
the charge pump can be left enabled while the regula-
tor is disabled. This avoids the delay that may other-
wise be required for the charge pump to reach full
operating voltage after being disabled. The CMOS
LDO regulator features low quiescent current even at
full load, making it very suitable for power sensitive
applications.
A bandgap reference bypass pin is provided to further
minimize noise by connecting an external capacitor
between this pin and ground. Another, external, regula-
tor can be connected to the charge pump output pin
CS, if required.
The CM3702 is available in a 10-lead MSOP package,
with optional lead-free finishing and is ideal for space
critical applications.
PACKAGE / PINOUT DIAGRAM
Note: This drawing is not to scale.
CM3702-50MS/MR
10 Lead MSOP Package
10-Lead MSOP-10
1
2
3
4
10
9
8
7
DGND
VIN
CS
GND
CP-
CP+
VOUT
EN_CHIP
Top View
56
BYP
EN_LDO
370
2
50/5
0S
PIN DESCRIPTIONS
LEAD(S)
NAME
DESCRIPTION
1
DGND
Ground for the charge pump circuit. This should be connected to the system (noisy) ground.
2VIN
Input power source for the device. Since the charge pump draws current in pulses at the
250kHz internal clock frequency, a low-ESR input decoupling capacitor is usually required close
to this pin to ensure low noise operation.
3
CS
Charge pump output which is connected to the external reservoir capacitor CS. This should be a
low-ESR capacitor. When the voltage on this pin reaches about 5.8V then the charge pump
pauses until the voltage on this pin drops to about 5.7V. This gives rise to at least 100mV of 'rip-
ple' (the frequency and amplitude of this ripple depends upon values of CP and CS and also the
ESR of CS).
4
GND
Ground reference for all internal circuits except the charge pump. This pin should be connected
to a "clean" low-noise analog ground
5
BYP
Bypass input connected to the internal voltage reference of the LDO regulator. An external
bypass capacitor CBYP of 0.1uF may be added to minimize internal voltage reference noise and
maximize power supply ripple rejection.