
2004 California Micro Devices Corp. All rights reserved.
01/20/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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Fax: 408.263.7846
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www.calmicro.com
13
CM3112
PRELIMINARY
Application Information (cont’d)
Power Dissipation/Handling
The overall junction to ambient thermal resistance
(
θ
JA
) for device power dissipation (P
D
) consists prima-
rily of two paths in series. The first path is the junction
to the case (
θ
JC
) which is defined by the package style,
and the second path is case to ambient (
θ
CA
) thermal
resistance which is dependent on board layout. The
final operating junction temperature for any set of con-
ditions can be estimated by the following thermal equa-
tion:
T
JUNC
= T
AMB
+ P
D
(
θ
JC
) + P
D
(
θ
CA
)
= T
AMB
+ P
D
(
θ
JA
)
The CM3112-12 uses a SOT23-5 package. When this
package is mounted on a double sided printed circuit
board with two square inches of copper allocated for
"heat spreading", the resulting
θ
JA
is 175°C/W.
Based on a maximum power dissipation of 315mW
(2.1Vx150mA), with an ambient of 70°C the resulting
junction temperature will be:
T
JUNC
= T
AMB
+ P
D
(
θ
JA
)
= 70°C + 315mW (175°C/W)
= 70°C + 55°C = 125°C
Thermal characteristics were measured using a double
sided board with two square inches of copper area
connected to the GND pins for "heat spreading".
Measurements showing performance up to junction
temperature of 125°C were performed under light load
conditions (1mA). This allows the ambient temperature
to be representative of the internal junction tempera-
ture.
Note: The use of multi-layer board construction with
separate ground and power planes will further enhance
the overall thermal performance. In the event of no
copper area being dedicated for heat spreading, a
multi-layer board construction, using only the minimum
size pad layout, will provide the CM3112-12 with an
overall
θ
JA
of 175°C/W which allows up to 450mW to
be safely dissipated.
Input Capacitor
If the VIN pin is within a few inches of the main input fil-
ter, a capacitor may not be necessary. Otherwise an
input filter capacitor (C
IN
) of 0.1uF to 1uF will ensure
adequate filtering.
Enable/Disable
Whenever this input is taken low, the regulator pass
transistor is forced into a high impedance mode and an
internal discharge resistance (500
) will be applied
from the output to ground.
Power Good
This is an open drain output signal. It works as a sup-
ply voltage supervisor for the output voltage.
It is asserted when the output falls below 84% (when
2.5V<Vin<5.5V) of its nominal value. The signal
becomes inactive when the three following conditions
are met (valid) for more than 1-10ms:
a) EN > 1.5V
b) 2.5V < V
IN
< 5.5V
c) V
OUT
> 97% of V
OUTNOM