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參數(shù)資料
| 型號： | CLM7660 |
| 廠商： | CALOGIC LLC |
| 英文描述： | DC-to-DC Voltage Converter |
| 中文描述： | 型DC - DC電壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 110K |
| 代理商： | CLM7660 |
CLM7660
C ORPORATION
CIRCUIT DESCRIPTION
The CLM7660 is an excellent voltage doubler, the device has
all the characteristic with the exception of two inexpensive
10
μ
F polarized electrolytic external capacitors. Figure 3
demonstrates the most effective means of using the device as
a voltage doubler. Capacitor C
1
is charged to a voltage, V+,
for the half cycle when switches S
1
and S
3
are closed. (Note
Switches S
2
and S
4
are open during this half cycle.) During
the second half of the operation, switches S
2
and S
4
are
closed, with S
1
and S
3
open, thereby shifting capacitor C
1
negatively by V+ volts. Charge is then transferred from C
1
to
C
2
, such that voltage on C
2
is exactly V+, asumming ideal
switches and no load on C
2
.
The four switches in Figure 3 are MOS power switches, S
1
is
a P-Channel device, S
2
, S
3
and S
4
are N-Channel devices.
The major challenge with this approach while integrating the
switches, the substrates of S
3
and S
4
must always remain
reversed-biased with respect to their sources, but not so
much as to degrade their ON-resistances. In addition, at
circuit start-up, and under short circuit conditions (V
OUT
=V
+
),
the output voltage must be sensed and the substrate bias
adjusted accordingly. Failure to accomplish this will result in
high power losses and probable device latch-up.
The above problem is eliminated in the CLM7660 by a logic
network which senses the output voltage (V
OUT
) together with
the level translators, and switches the substrates of S
3
and S
4
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the CLM7660 is an integral
part of the anti-latch-up circuitry. Its inherent voltage drop can
degrade operation at low voltages. To improve low-voltage
operation, the LV pin should be connected to GND, disabling
the regulator. For supply voltages greater than 3.5V, the LV
terminal must be left open to ensure latch-up proof operation
and prevent device damage.
THEORETICAL POWER EFFICIENCY CONSIDERATIONS
In theory, a voltage multiplier can approach 100% efficiency if
certain conditions are met:
1. The drive circuitry consumes minimal power.
2. The output switches have extremely low ON-resistance and
virtually no offset.
3. The impedances of the pump and reservoir capacitors are
negligible at the pump frequency.
When larger values of C
1
and C
2
are used, the CLM7660
approaches the above conditions for negative voltage
multiplication. Energy is lost only if the transfer of the charge
between capacitors if a change in voltage occurs. The energy
lost is defined by:
E=1/2C
1
(V
1
2-V
2
2)
During the pump and transfer cycles V
1
and V
2
are the
voltages on C
1
. If the impedances of C
1
and C
2
are high at
the pump frequency (see Figure 3), compared to the value of
R
L
, there will be a substantial difference in voltages V
1
and
V
2
. The most optimum selection would be to make C
2
as
large as possible to eliminate output voltage ripple, and to
utilize a large value for C
1
to achieve maximum efficiency of
operation.
OPERATIONAL RULES:
Never exceed maximum supply voltages.
Never connect LV terminal to GND for supply voltages over
3.5V.
Never short circuit the output to V
+
supply voltages above
5.5V for extended periods; however, transient conditions
including start-up are acceptable.
For polarized capacitors, the + terminal of C
1
must be
connected to pin 2 of the CLM7660 and the + terminal to of C
2
must be connected to GND.
For high-voltage, elevated temperature applications add a
diode D
X
(reference Figure 1). The 1N914 diode is an
appropriate choice.
CALOGIC CORPORATION,
237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
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