參數(shù)資料
型號(hào)： CLC952AJMSA
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： CLC949ACQ
中文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝： SSOP-28
文件頁數(shù)： 7/8頁
文件大小： 233K
代理商： CLC952AJMSA
AGND
(Pins 1, 6, 13) Analog circuit ground.
AV
CC
(Pins 2, 12, 14) +5V power supply for the analog section. Bypass to analog ground with a 0.1
μ
F capacitor.
AV
EE
(Pins 3, 5, 7,11) -5V power supply for the analog section. Bypass to analog ground with a 0.1
μ
F capacitor.
ENCODE
(Pin 4) ENCODE initiates a new data conversion cycle on each rising edge. Logic for this input is
standard TTL. 50% duty cycle is recommended for full compliance with the guaranteed specifications.
AIN
(Pin 8) Ground-centered, DC-coupled analog input with a 1V
pp
maximum input range from -0.5V to
+0.5V. Analog input impedance is approximately 500
.
V
OFFSET
(Pin 9) Voltage offset control. Sets the midpoint of the analog input range. Normally left floating. Ratio
of applied voltage to effective offset is 200:1. (1V applied to V
OFFSET
produces 5mV midpoint offset.)
V
REF
(Pin 10) Internal voltage reference. Nominally +2.4V. V
REF
can be pulled up or down with a voltage
source to program gain and input range. Bypass V
REF
to ground with a 0.1
μ
F capacitor.
DV
CC
(Pin 15) +5V power supply for the digital section. Bypass to digital ground with a 0.1
μ
F capacitor.
DGND
(Pin 16) Digital ground.
D0-D11
___
(Pins 17-28) Digital data outputs are CMOS and TTL compatible. D0 is the LSB and D11
MSB is inverted. Output coding is two’s complement.
___
is the MSB.
1
AGND
28
D11 (MSB INV)
2
AV
CC
27
D10
3
AV
EE
26
D9
4
ENCODE
25
D8
5
AV
EE
24
D7
6
AGND
23
D6
7
AV
EE
22
D5
8
AIN
21
D4
9
V
OFFSET
20
D3
10
V
REF
19
D2
11
AV
EE
18
D1
12
AV
CC
17
D0 (LSB)
13
AGND
16
DGND
14
AV
CC
15
DV
CC
CLC952
CLC952 Pin Definitions
7
http://www.national.com
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