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參數(shù)資料
| 型號(hào)： | CLC949 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| 中文描述： | 極低功耗，12位，20MSPS單片A / D轉(zhuǎn)換Convertter |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 737K |
| 代理商： | CLC949 |
5
http://www.national.com
CLC949 OPERATION
Application
In a high speed data acquisition system, the overall
performance is often determined by the A/D converter
and its surrounding circuitry. You should pay special
attention to the data converter and its support circuitry if
you want to obtain the best possible performance. The
information on these pages is intended to help you
design the circuitry surrounding the CLC949 in such
a way as to achieve superior results. Additional
information is available in the form of Comlinear
applications notes. Especially useful are AD-01 and
AD-02.
Circuit Description
The CLC949 ADC consists of an input Sample-and-Hold
Amplifier (SHA) followed by a pipelined quantizer.
Internal reference sources and output data latches
complete the major functions required of an A/D
converter. Digital error correction in the quantizer helps
to provide accurate conversions of high speed dynamic
signals. The speed of the analog circuitry is determined
in part by the internal bias currents applied. The CLC949
allows you to make this important tradeoff between
power and performance through settings on two digital
control pins and for fine adjustments through the use of
an external resistor.
Timing and CLK Generation
The falling edge of the CLK pulse causes the input sam-
ple-and-hold amplifier to transition into the hold mode.
The sample is taken approximately 3ns after this falling
edge. The digitized data is presented to the output latch-
es 6 1/2 clock cycles later and is held until after the next
rising edge of CLK. This timing is shown in the timing
diagram, Figure 1.
Figure 1: Timing Diagram
The CLC949 is designed to operate with a CMOS clock
signal. To obtain the lowest possible noise when
digitizing a high frequency input, more care must be
taken in the generation of this clock than is usually
accorded to CMOS Clocks. To minimize aperture jitter
induced errors, the CLK needs to have as low a
jitter as possible and as fast an edge rate as possible. To
obtain a very low jitter clock from a sinusoidal source, the
circuit shown in Figure 2 is recommended.
Figure 2: Clock Generation
Here the CLC006 cable driver is used as a comparator to
generate a high speed clock. The CLC006 has less than
2ps of jitter and has rise and fall times less than 1ns. The
CLC006 output is then buffered by a 74AC04 which
maintains fast edge rates and provides CMOS levels for
the CLC949. If there is excessive jitter in the CLK, then
the digitized signal will exhibit an excessive amount of
noise, especially for high frequency inputs. For a more
detailed description of this phenomenon, please read the
Comlinear Application Note AD-03.
In addition to the circuitry generating the clock, the
layout of the clock distribution network can affect the
overall performance of the converter. To obtain the best
possible performance, a clock driver with very low output
impedance and fast edge rates such as the 74AC04,
should be placed as close as possible to the CLC949
clock input pin. Additional length in the circuit trace for
the clock will cause an increase in the jitter seen by the
converter.
On the CLC949 evaluation board, the
E949PCASM, there is less than 1/16th of an inch
between the 74AC04 that is driving the clock input and
the input to the CLC949. If the system has several
CLC949s, and jitter is liable to generate problems, then
use a separate clock driver for each CLC949. Each
driver should be placed as close to the converter that it is
driving as is practicable.
Driving the Differential Input
The CLC949 has a differential input with a common
mode voltage of 2.25V. Since not all applications have a
signal preconditioned in this manner there is often a need
to do a single-ended-to-differential conversion and to add
offset. In systems which do not need to be DC coupled,
the best method for doing this is with an RF transformer
such as the Minicircuits TMO1-1T. This is an RF
transformer with a center tapped secondary which will
operate over a frequency range of 50kHz to 200MHz.
You can offset the input and split the phases simply by
connecting the center tap to the mid scale reference
output (V
REFMO
) as shown in Figure 3.
This set up can be realized on the CLC949 evaluation
board by enabling option 1. See E949PCASM data
sheet for details. A transformer coupled input will allow
the CLC949 to exhibit the best possible distortion
performance for high frequency input signals.
Analog
Input
CLK
Output
Data
Effective Aperture Delay
Output Hold Time
Sample 0
Sample 1
Sample 2
Sample
3
Sample 4
Sample
5
Sample 6
Sample 7
-3 Valid
-2 Valid
-1 Valid
0 Valid
Sinusoisal
Clock Input
50
9
3
1
4
6
+5V
+
CLC006
-
50
1k
0.1
μ
F
10k
0.1
μ
F
2.2k
2.2k
8
5
10k
10k
+5V
0.1
μ
F
74AC04
To CLC949
Clock
1k
+5V
相關(guān)PDF資料 |
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| CLC949ACQ | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| CLC949AJQ | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| CLC952PCASM | CLC949ACQ |
| CLC952 | CLC949ACQ |
| CLC952ACMSA | CLC949ACQ |
相關(guān)代理商/技術(shù)參數(shù) |
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| CLC949ACQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| CLC949AJQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| CLC952 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CLC949ACQ |
| CLC952 WAF | 制造商:Texas Instruments 功能描述: |
| CLC952ACMSA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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