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參數(shù)資料
| 型號(hào)： | CLC935BC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-bit, 15MSPS A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP40 |
| 封裝： | 1.100 INCH, SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 271K |
| 代理商： | CLC935BC |
http://www.national.com
8
analog input range =
± [2V + (0.129)(V
GAIN ADJUST
- 2.5V)]
GAIN ADJUST pin(33)
Voltage
1.0V
2.5V or open
4.0V
Analog Input Range
1.8V
pp
2.0V
pp
2.2V
pp
Analog Input Range Adjust Circuit
A resistor from GAIN ADJUST to ground provides a
second method of adjusting the analog input range. This
technique will decrease the data converter’s gain and
increase the analog input range.
Alternate Input Range Adjust Circuit
Offset Adjust
Typically the center of the ±1V analog input range is laser
trimmed to 0V during construction. By applying a voltage
at the OFFSET ADJUST (pin 36), the analog input offset
can be adjusted approximately ±100mV around ground.
The applied voltage at pin 36 can range from GROUND
to V
OFFSET REFERENCE
. If the OFFSET REFERENCE
(pin 37) voltage is used to generate the applied OFFSET
ADJUST voltage, adjustments in the analog input
range offset will track any adjustments made to the
analog input range gain. Analog input range gain and
offset adjustments are tightly coupled when the OFFSET
REFERENCE is used to generate the OFFSET ADJUST
applied voltage. Self-calibration techniques for adjusting
offset and gain should use OFFSET REFERENCE in
adjusting the offset.
Analog input offset and gain adjustments can be made
independent of each other if the VREF OUT (pin 35) is
used to generate the applied OFFSET ADJUST voltage
instead of the OFFSET REFERENCE voltage. If the
VREF OUT approach is adopted, the CLC935 offset and
gain will be independent of each other, but will likely need
an iterative adjustment approach where both offset and
gain are successively adjusted until the desired result is
obtained.
Offset Adjust Range
pin (36)
V
OFFSET REFERENCE
open
GROUND
Analog Input Offset
+100mV
0mV
-100mV
Offset Adjust Circuit
The OFFSET ADJUST and GAIN ADJUST pins are
sensitive to noise; and should be bypassed to ground
with 0.1
μ
F ceramic capacitors. If the OFFSET ADJUST
and GAIN ADJUST pins are not used, then they should
be left floating.
CONVERT Clock Generation
All high-speed high-resolution A/D converters are sensi-
tive to the CONVERT clock quality. With a full scale
7MHz analog input signal, the slew rate at the 0V cross-
ing is 90LSB/ns. An error (jitter) of as little as 5ps in the
clock edge will yield a 0.5LSB error at the A/D output.
This is as great or greater than any other error source
likely to be present. This type of clock error or clock jitter
is most easily seen in the form of poor SNR (signal-to-
noise ratio). If the SNR is below expectations, clock jitter
should be investigated.
It should also be noted that jitter in the analog input
source will have the same detrimental effect on SNR.
Analog input signal jitter is usually only a problem in
evaluation setups, and does not generally present a
problem in full systems.
Low-jitter crystal controlled oscillators make the best
CONVERT clock sources. If the CONVERT clock is
dividing or other method, it should be registered by the
original clock as the last step. This should keep jitter
terms from compounding.
2.500V
1K
GAIN
ADJUST
35
33
0.500V
250
680
2K
2.7k
OP14
100
0.1
μ
F
GAIN ADJUST
RANGE
1.0V
to
4.0V
CLC935
+
_
V
REF
OUT
GAIN
ADJUST
33
CLC935
R
R =
774 - 4,800
Where
is the gain change factor,
i.e 0.01 equals 1% change.
V
, pin (37) is
nominally +3.1 V and
ranges from +3.4V to
+2.8V depending on
the specific GAIN
ADJUST voltage
at pin 33.
OFFSET
ADJUST
36
OP14
100
0.1
CLC935
OFFSET
REFERENCE
37
2K
1.5K
Offset Adjust Range
V
offset
REF
, to
(V
offset
REF
, – 1.8V);
1.3V to 3.1V.
SNR
20log
1
2 f jitter
where:
jitter
clock jitter
analog jitter
MAX
RMS
RMS
RMS
2
RMS
2
=
=
(
)
+
(
)
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