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參數(shù)資料
| 型號(hào)： | CLC5958PCASM |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 14-bit, 52MSPS A/D Converter |
| 中文描述： | 14位，52MSPS A / D轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 1614K |
| 代理商： | CLC5958PCASM |
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8
Driving the Analog Inputs
The differential analog inputs, AIN and AIN, are biased
from an internal 3.25V reference (a 2.4V bandgap
reference plus a diode) through an on-chip resistance of
500
. This bias voltage is set for optimum performance,
and varies with temperature. Since DC coupling the
inputs overrides the internal common mode voltage, it is
recommended that the inputs to the CLC5958 be AC
coupled whenever possible. The time constant of the
input coupling network must be greater than 1
μ
sec to
minimize distortion due to nonlinear input bias currents.
Additionally, the common mode source impedance
should be less than 100
at the sample rate.
If DC coupling is required, then the V
CM
output may be
used to establish the input common mode voltage. The
CLC5958 samples the common mode voltage at the
internal track-and-hold output and servos the V
CM
output
to establish the optimum common mode potential at the
track-and-hold. It is possible to use the V
CM
output to
construct an external servo loop.
Figure 1 below illustrates one input coupling method. The
transformer
provides
noiseless
differential conversion. The two 50
resistors in the
secondary define the input impedance and provide a low
common mode source impedance through the bypass
capacitors.
single-ended
to
Figure 1: Input Coupling
Alternatively, the inputs can be driven using a differential
amplifier as shown in Figure 2.
The network of Figure 2 uses a simple RC low-pass filter
to roll off the noise of the differential amplifier. The net-
work has a cutoff frequency of 40MHz. Different noise
filter designs are required for different applications. For
example, an IF application would require a band-pass
noise filter.
The analog input lines should be routed close together so
that any coupling from other sources is common mode.
Figure 2: Differential Amplifier
Driving the ENCODE Inputs
The ENCODE and ENCODE inputs are differential clock
inputs that are referenced to V
CC
. They may be driven
with PECL input levels. Alternatively they may be driven
with a differential input (e.g. a sine input) that is centered
at 1.2 Volts below V
CC
and which meets the min and max
ratings for V
IL
and V
IH
. Low noise differential clock signals
provide the best SNR performance for the converter.
The ENCODE inputs are not self biasing, so a DC bias
current path must be provided to each of the inputs.
Figure 3 shows one method of driving the encode inputs.
Figure 3: ENCODE Inputs
The transformer converts the single-ended clock signal to
a differential signal. The center-tap of the secondary is
biased by the V
BB
potential of the ECL buffer. The diodes
in the secondary limit the input swing to the buffer.
Since the encode inputs are close to the analog inputs, it
is recommended that the analog inputs be routed on the
top of the board directly over a ground plane and that the
encode lines be routed on the back of the board and then
connected through via to the encode inputs.
Latching the Output Data
The rising edge of DAV is approximately centered in the
data transition window, and may be used to latch the
output data. The DAV output has twice the load driving
capability of the data outputs so that two latch clock
inputs may be driven by this output.
CLC5958 Application Information
VIN
AIN
AIN
CLC5958
50
50
0.1
0.1
0.1
0.01
0.1
1:1.4
AIN
AIN
CLC5958
39pf
39pf
0.1
0.1
100
100
VIN
VIN
ENCODE
ENCODE
CLC5958
332
332
D
D
Q
Q
V
BB
Clock
0.1
1:1
0.1
25
25
MC10EL16
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