參數(shù)資料
型號(hào): CLC5956IMTD
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 12-bit, 65 MSPS Broadband Monolithic A/D Converter
中文描述: 1-CH 12-BIT CONVERTER SUBSYSTEM ADC, PARALLEL ACCESS, PDSO48
封裝: TSSOP-48
文件頁(yè)數(shù): 9/10頁(yè)
文件大?。?/td> 391K
代理商: CLC5956IMTD
Evaluation Printed Circuit Board
The Evaluation board for the CLC5956 allows for easy test
and evaluation of the product. The part may be ordered with
all components loaded and tested. The order number is the
CLC5956PCASM. The user supplies an analog input signal,
encode signal and power to the board and is able to take
latched 12-bit digital data out of the board.
ENCODE Input (ENC)
The ENCODE input is an SMA connector with a 50
termi-
nation. The signal is converted from single to differential and
its
frequency is divided by four
to produce a low jitter, sym-
metrical encode signal for the CLC5956. The user should
provide a sinusoidal or square wave signal of 10 dBm to
16 dBm amplitude at
four times the converter’s desired
sample rate
. It is recommended that the source be low jitter
to maintain best performance. The transformer will pass sig-
nals in the 40 MHz to 260 MHz range which allows sample
rates of 10 Msps to 65 Msps.
Clock Option
The CLC5956 board is configured for a 4x clock input to pro-
vide optimal performance with some (i.e., HP8662) synthe-
sizers. The HP8662 output has lower jitter above 160 MHz.
Using a 208 MHz clock to sample at 52 MHz minimizes the
effect of the synthesizer on the measurement.
To use a 1x clock, replace the divide-by-4 sine-to-PECL con-
verter
(U4,
MC10EL33D)
with
MC10EL16D sine-to-PECL converter does not divide the
clock. This approach would be suitable for use with a synthe-
sizer that has optimal jitter performance at 52 MHz (i.e.,
HP8643 or HP8644).
The best ADC performance is obtained with a low-jitter crys-
tal oscillator module installed at Y1 on the evaluation board.
an
MC10EL16D. The
U4 should be replaced with an MC10EL16D. Placing the
clock source on the evaluation board reduces ground loop
issues and thus improves performance.
Analog Input (AIN)
The analog input is an SMA connector with a 50
termina-
tion. The signal is converted from single to differential by a
transformer with a 5 MHz to 260 MHz bandwidth and ap-
proximately one dB loss. Full scale is approximately 11 dBm
or 2.2 V
. It is recommended that the source for the analog
input signal be low jitter, low noise and low distortion to allow
for proper test and evaluation of the CLC5956.
Supply Voltages (J1 pins 31 A&B
and 32 A&B)
The CLC5956PCASM is powered from a single 5V supply
connected from the referenced pins on the Eurocard con-
nector. The recommended supplies are low noise linear sup-
plies.
Digital Outputs (J1 pins 7A (MSB,
D11), 8B (D10) through 18B (LSB)
and 20B (Data Ready)
The digital outputs are provided on the Eurocard connector.
The outputs are buffered by 5V CMOS latches with 50
se-
ries output resistors. The rising edge of Data Ready may be
used to clock the output data into data collection cards or
logic analyzers. The board has a location for the HP
01650-63203 termination adapter for HP 16500 logic analyz-
ers to simplify connection to the analyzer.
www.national.com
9
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PDF描述
CLC5956IMTDX 12-bit, 65 MSPS Broadband Monolithic A/D Converter
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CLC5956IMTDX 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-bit, 65 MSPS Broadband Monolithic A/D Converter
CLC5956PCASM 功能描述:EVALUATION BOARD FOR CLC5956 RoHS:是 類別:編程器,開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率(每秒):94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源(標(biāo)準(zhǔn)):- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板,軟件
CLC5957 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit, 70MSPS Broadband Monolithic A/D Converter
CLC5957_02 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit, 70MSPS Broadband Monolithic A/D Converter
CLC5957MTD 制造商:Texas Instruments 功能描述:IC 12BIT ADC 70MSPS BB MONOLITHIC