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參數(shù)資料
| 型號： | CLC5955MTDX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
| 中文描述： | 1-CH 11-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 197K |
| 代理商： | CLC5955MTDX |
http://www.national.com
8
Analog Inputs and Bias
Figure 1 depicts the analog input and bias scheme. Each
of the differential analog inputs are internally biased to a
nominal voltage of 2.40 volts DC through a 500
resistor
to a low impedance buffer. This enables a simple
interface to a broadband RF transformer with a center-
tapped output winding that is decoupled to the analog
ground. If the application requires the inputs to be DC
coupled, the V
cm
output can be used to establish the
proper common -mode input voltage for the ADC. The
V
cm
voltage reference is generated from an internal
bandgap source that is very accurate and stable.
Figure 1: CLC5955 Bias Scheme
The V
cm
output may also be used to power down the
ADC. When the V
cm
pin is pulled above 3.5V, the internal
bias mirror is disabled and the total current is reduced to
less than 10mA. Figure 2 depicts how this function can
be used. The diode is necessary to prevent the logic gate
from altering the ADC bias value.
Figure 2: Power Shutdown Scheme
ENCODE Clock Inputs
The CLC5955’s differential input clock scheme is
compatible with all commonly used clock sources.
Although small differential and single-ended signals are
adequate, for best aperture jitter performance a low noise
differential clock with a high slew rate is preferred. As
depicted in Figure 3, both ENCODE clock inputs are
internally biased to V
CC
/2 though a pair of 5K resistors.
The clock input buffer operates with any common-mode
voltage between the supply and ground.
Figure 3: CLC5955 ENCODE Clock Inputs
The internal bias resistors simplify the clock interface to
another center-tapped transformer as depicted in Figure
4. A low phase noise, RF synthesizer of moderate ampli-
tude (1 - 4V
pp
) can drive the ADC through this interface.
Figure 4: Transformer Coupled Clock Scheme
V
cm
1.23V
Bandgap
Reference
ADC
Bias Mirror
2K
To T/H
and ADC
A
in
A
in
2.4V
5
μ
–
+
-
500
500
V
ref
5V CMOS
"1" = on
"0" = off
CLC5955
BJT Current Mirror
V
CCA
GNDA
ENC
ENC
5k
5k
5k
5k
ENC
ENC
CLC5955
~
CLC5955 Applications
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| CLC5956IMTD | 12-bit, 65 MSPS Broadband Monolithic A/D Converter |
| CLC5956IMTDX | 12-bit, 65 MSPS Broadband Monolithic A/D Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5955MTDX/NOPB | 功能描述:ADC 11BIT 55MSPS 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| CLC5956 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-bit, 65 MSPS Broadband Monolithic A/D Converter |
| CLC5956IMTD | 功能描述:IC CONV A/D 12BIT MONO 48-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| CLC5956IMTDX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-bit, 65 MSPS Broadband Monolithic A/D Converter |
| CLC5956PCASM | 功能描述:EVALUATION BOARD FOR CLC5956 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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