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參數(shù)資料
| 型號： | CLC5955 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
| 中文描述： | 11位，55MSPS寬帶單片A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 197K |
| 代理商： | CLC5955 |
CLC5955
9
http://www.national.com
Figures 5 shows the clock interface scheme for square
wave clock sources.
Figure 5: TTL, 3V or 5V CMOS Clock Scheme
Figure 6: CLC5955 Digital Outputs
Digital Outputs and Level Select
Figure 6 depicts the digital output buffer and bias used in
the CLC5955. Although each of the eleven output bits
uses a controlled current buffer to limit supply transients,
it is recommended that parasitic loading of the outputs is
minimized. Because these output transients are harmoni-
cally related to the analog input signal, excessive loading
will degrade ADC performance at some frequencies.
The logic high level is slaved to the internal 2.4 voltage
reference. The OUTLEV control pin selects either a 3.3V
or 2.5V logic high level. An internal pullup resistor selects
the 3.3 volt level as the default when the OUTLEV pin is
left open. Grounding the OUTLEV pin selects the 2.5V
logic high level.
To ease user interface to subsequent digital circuitry, the
CLC5955 has a data valid clock output (DAV). In order to
match delays over IC processing variables, this digital
output also uses the same output buffer as the data bits.
The DAV clock output is simply a delayed version of the
ENCODE input clock. Since the ADC output data change
is slaved to the falling edge of the ENCODE clock, the
rising DAV clock edge occurs near the center of the data
valid window (or eye) regardless of the sampling frequency.
Minimum Conversion Rate
This ADC is optimized for high-speed operation. The
internal bipolar track and hold circuits will cause droop
errors at low sample rates. The point at which these
errors cause a degradation of performance is listed on
the specifications page as the minimum conversion rate.
If a lower sample rate is desired, the ADC should be
clocked at a higher rate, and the output data should be
decimated. For example, to obtain a 10MSPS output, the
ADC should be clocked at 20MHz, and every other output
sample should be used. No significant power savings
occurs at lower sample rates, since most of the power is
used in analog circuits rather than digital circuits.
ENC
CLC5955
0.01
μ
F
0.01
μ
F
ENC
.4V
ref
GNDD
Digital
V
CCD
Controlled Current
Output Buffer
Digital
Output
Output
Open = 3.3V
hi
GND = 2.5V
hi
CMOS
+
-
+
-
10k
50
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC5955MTDX | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
| CLC5956PCASM | 12-bit, 65 MSPS Broadband Monolithic A/D Converter |
| CLC5956 | 12-bit, 65 MSPS Broadband Monolithic A/D Converter(12位65 MSPS寬帶單片A/D轉(zhuǎn)換器) |
| CLC5956IMTD | 12-bit, 65 MSPS Broadband Monolithic A/D Converter |
| CLC5956IMTDX | 12-bit, 65 MSPS Broadband Monolithic A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5955MTD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| CLC5955MTD/NOPB | 功能描述:ADC 11BIT 55MSPS 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| CLC5955MTDX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:11-bit, 55MSPS Broadband Monolithic A/D Converter |
| CLC5955MTDX/NOPB | 功能描述:ADC 11BIT 55MSPS 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| CLC5956 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-bit, 65 MSPS Broadband Monolithic A/D Converter |
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