參數(shù)資料
型號: CLC5623IN
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運動控制電子
英文描述: Triple, High Output, Video Amplifier
中文描述: TRIPLE OP-AMP, 8000 uV OFFSET-MAX, PDIP8
封裝: PLASTIC, DIP-8
文件頁數(shù): 7/12頁
文件大?。?/td> 182K
代理商: CLC5623IN
DC Coupled Single Supply Operation
Figures 1 and 2 show the recommended non-inverting
and inverting configurations for input signals that remain
above 0.8V DC.
Figure 1: Non-Inverting Configuration
Figure 2: Inverting Configuration
AC Coupled Single Supply Operation
Figures 3 and 4 show possible non-inverting and invert-
ing configurations for input signals that go below 0.8V
DC. The input is AC coupled to prevent the need for
level shifting the input signal at the source. The resistive
voltage divider biases the non-inverting input to V
CC
÷ 2
= 2.5V (For V
CC
= +5V).
Figure 3: AC Coupled Non-Inverting Configuration
Figure 4: AC Coupled Inverting Configuration
Dual Supply Operation
The CLC5623 operates on dual supplies as well as
single supplies. The non-inverting and inverting configu-
rations are shown in Figures 5 and 6.
Figure 5: Dual Supply Non-Inverting Configuration
Figure 6: Dual Supply Inverting Configuration
7
http://www.national.com
+
-
1/3
CLC5623
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
in
R
g
R
t
5
6
11
4
7
V
V
A
1
R
R
o
in
v
f
g
=
= +
V
cm
V
CC
R
L
V
cm
Note:
R
, R
and R
are tied
to V
for minimum power
consumption and maximum
output swing.
V
cm
+
-
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
in
R
b
11
R
g
V
V
A
R
R
o
in
v
f
g
=
=
R
t
5
6
V
cm
V
CC
R
L
V
cm
Note:
R
, provides DC bias
for non-inverting input.
R
b
, R
L
and R
are tied
to V
for minimum power
consumption and maximum
output swing.
V
cm
Select R
t
to yield
desired R
in
= R
t
|| R
g
1/3
CLC5623
4
7
+
-
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
in
R
g
C
R
11
C
c
R
V
V
1
R
R
2.5
o
in
f
g
=
+
+
low frequency cutoff
1
2 R C
, where: R
R
2
c
in
=
=
R
R
source
>>
5
6
V
CC
V
CC
2
1/3
CLC5623
4
7
7
4
+
-
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
in
R
11
C
c
R
V
V
R
R
2.5
o
in
f
g
=
+
low frequency cutoff
1
2 R C
c
=
R
g
5
6
V
CC
V
CC
2
1/3
CLC5623
+
-
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
in
V
CC
0.1
μ
F
6.8
μ
F
V
EE
5
6
11
+
R
g
R
t
V
V
A
1
R
R
o
in
v
f
g
=
= +
1/3
CLC5623
4
7
+
-
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
in
V
CC
0.1
μ
F
6.8
μ
F
V
EE
R
g
R
b
5
6
11
+
R
t
R
b
provides DC bias
Note:
Select R
to yield desired
R
in
= R
t
|| R
g
.
V
V
A
R
R
o
in
v
f
g
=
=
1/3
CLC5623
4
7
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