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參數(shù)資料
| 型號： | CLC5623IM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | Triple, High Output, Video Amplifier |
| 中文描述： | TRIPLE OP-AMP, 8000 uV OFFSET-MAX, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 182K |
| 代理商： | CLC5623IM |
9
http://www.national.com
Figure 10:Transmission Line Matching
Inverting gain applications:
I
Connect R
3
directly to ground.
I
Make the resistors R
4
, R
6
, and R
7
equal to Z
o
.
I
Make R
5
II R
g
= Z
o
.
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C
6
to match the output transmission line over a
greater frequency range. C
6
compensates for the increase
of the amplifier’s output impedance with frequency.
Power Dissipation
Follow these steps to determine the power consumption
of the CLC5623:
1. Calculate the quiescent (no-load) power:
P
amp
= I
CC
(V
CC
- V
EE
)
2. Calculate the RMS power at the output stage:
P
o
= (V
CC
- V
load
) (I
load
), where V
load
and I
load
are the RMS voltage and current across the
external load.
3. Calculate the total RMS power:
P
t
= P
amp
+ P
o
The maximum power that the DIP and SOIC packages
can dissipate at a given temperature is illustrated in
Figure 11. The power derating curve for any CLC5623
package can be derived by utilizing the following
equation:
(175
°
θ
where
T
amb
= Ambient temperature (°C)
θ
JA
= Thermal resistance, from junction to ambient,
for a given package (°C/W
Figure 11: Power Derating Curves
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance.
evaluation boards for the CLC5623 (CLC730075-DIP,
CLC730074-SOIC) and suggests their use as a guide for
high frequency layout and as an aid for device testing and
characterization.
National provides
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
I
Include 6.8
μ
F tantalum and 0.1
μ
F ceramic
capacitors on both supplies.
I
Place the 6.8
μ
F capacitors within 0.75 inches
of the power pins.
I
Place the 0.1
μ
F capacitors less than 0.1 inches
from the power pins.
I
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
I
Minimize all trace lengths to reduce series
inductances.
I
Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.
Evaluation Board Information
A data sheet is available for the CLC730075/ CLC730074
evaluation boards.
The evaluation board data sheet
provides:
I
Evaluation board schematics
I
Evaluation board layouts
I
General information about the boards
The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation.
For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for National’s
monolithic amplifiers that:
I
Support Berkeley SPICE 2G and its many derivatives
I
Reproduce typical DC, AC, Transient, and Noise
performance
I
Support room temperature simulations
The
readme
file that accompanies the diskette lists
released models, and provides a list of modeled parame-
ters.
The application note OA-18, Simulation SPICE
Models for National’s Op Amps, contains schematics and
a reproduction of the readme file.
P
Ambient Temperature (
°
C)
0
0.2
0.4
0.6
0.8
1.0
-40 -20
0
20
40
60
80 100 120
180
IN
IM
140 160
T
amb
JA
)
+
-
R
3
Z
0
R
6
V
o
Z
0
R
1
R
2
+
R
g
Z
0
R
4
R
5
V
1
V
2
+
R
f
C
6
R
7
1/3
CLC5623
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5623IMX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CLC5623IN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CLC5623M WAF | 制造商:Texas Instruments 功能描述: |
| CLC5632 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual, High Output, Programmable Gain Buffer |
| CLC56321MX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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