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參數(shù)資料
| 型號(hào)： | CLC5612IN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Dual, High Output, Programmable Gain Buffer |
| 中文描述： | DUAL BUFFER AMPLIFIER, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 208K |
| 代理商： | CLC5612IN |
9
http://www.national.com
Non-inverting gain applications:
I
Connect pin 2 as indicated in the table in the
Closed Loop Gain Selection
section.
I
Make R
1
, R
2
, R
6
, and R
7
equal to Z
o
.
I
Use R
3
to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.
Inverting gain applications:
I
Connect R
3
directly to ground.
I
Make the resistors R
4
, R
6
, and R
7
equal to Z
o
.
I
Make R
5
II R
g
= Z
o
.
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C
6
to match the output transmission line over a
greater frequency range. C
6
compensates for the increase
of the amplifier’s output impedance with frequency.
Figure 11:Transmission Line Matching
Power Dissipation
Follow these steps to determine the power consumption
of the CLC5612:
1. Calculate the quiescent (no-load) power:
P
amp
= I
CC
(V
CC
- V
EE
)
2. Calculate the RMS power at the output stage:
P
o
= (V
CC
- V
load
) (I
load
), where V
load
and I
load
are the RMS voltage and current across the
external load.
3. Calculate the total RMS power:
P
t
= P
amp
+ P
o
The maximum power that the DIP and SOIC,
packages can dissipate at a given temperature is
illustrated in Figure 12. The power derating curve for
any CLC5612 package can be derived by utilizing the
following equation:
°
θ
where
T
amb
= Ambient temperature (°C)
θ
JA
= Thermal resistance, from junction to ambient,
for a given package (°C/W)
Figure 12: Power Derating Curve
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance.
evaluation boards for the CLC5612 (CLC730038-DIP,
CLC730036-SOIC) and suggests their use as a guide for
high frequency layout and as an aid for device testing and
characterization.
Comlinear provides
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
I
Include 6.8
μ
F tantalum and 0.1
μ
F ceramic
capacitors on both supplies.
I
Place the 6.8
μ
F capacitors within 0.75 inches
of the power pins.
I
Place the 0.1
μ
F capacitors less than 0.1 inches
from the power pins.
I
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
I
Minimize all trace lengths to reduce series
inductances.
I
Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.
Evaluation Board Information
A data sheet is available for the CLC730038/ CLC730036
evaluation boards.The evaluation board data sheets pro-
vide:
I
Evaluation board schematics
I
Evaluation board layouts
I
General information about the boards
The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation.
For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.
(175
T
amb
JA
)
1
7
6
8
5
3
4
2
1k
+
-
+
-
1k
1k
1k
CLC5612
Z
0
R
6
V
o
Z
0
R
4
R
5
+
R
3
Z
0
R
1
R
2
V
1
V
2
+
C
6
R
7
Note:
Channel 2 not shown.
P
Ambient Temperature (
°
C)
0
0.2
0.4
0.6
0.8
1.0
-40 -20
0
20
40
60
80 100 120
180
IN
IM
140 160
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