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參數(shù)資料
| 型號： | CLC5612 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual, High Output, Programmable Gain Buffer |
| 中文描述： | 雙路，高輸出，可編程增益緩沖器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 208K |
| 代理商： | CLC5612 |
7
http://www.national.com
The gain accuracy of the CLC5612 is excellent and
stable over temperature change.
setting resistors, R
f
and R
g
are diffused silicon resistors
with a process variation of ± 20% and a temperature
coefficient of 2000ppm/°C.
values change with processing and temperature, their
ratio (R
f
/R
g
) remains constant. If an external resistor is
used in series with R
g
, gain accuracy over temperature
will suffer.
The internal gain
Although their absolute
Single Supply Operation (V
CC
= +5V,V
EE
= GND)
The specifications given in the
+5V Electrical Character-
istics
table for single supply operation are measured with
a common mode voltage (V
cm
) of 2.5V. V
cm
is the volt-
age around which the inputs are applied and the
output voltages are specified.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5612 is typically +0.8V to
+4.2V. The typical output range with R
L
=100
is +1.0V
to +4.0V.
For single supply DC coupled operation, keep input
signal levels above 0.8V DC. For input signals that drop
below 0.8V DC, AC coupling and level shifting the signal
are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in
the following 2 sections.
DC Coupled Single Supply Operation
Figures 1, 2, and 3 on the following page, show the
recommended configurations for input signals that
remain above 0.8V DC.
Figure 1: DC Coupled, A
v
= -1V/V Configuration
Figure 2: DC Coupled, A
v
= +1V/V Configuration
Figure 3: DC Coupled, A
v
= +2V/V Configuration
AC Coupled Single Supply Operation
Figures 4, 5, and 6 show possible non-inverting and invert-
ing configurations for input signals that go below 0.8V DC.
Figure 4: AC Coupled, A
v
= -1V/V Configuration
The input is AC coupled to prevent the need for
level shifting the input signal at the source. The resistive
voltage divider biases the non-inverting input to V
CC
÷ 2
= 2.5V (For V
CC
= +5V).
Figure 5: AC Coupled, A
v
= +1V/V Configuration
1
7
6
8
5
3
4
2
1k
+
-
+
-
1k
1k
1k
CLC5612
0.1
μ
F
6.8
μ
F
+
V
o
V
in
R
b
R
t
V
cm
V
CC
R
L
V
cm
Note:
R
b
provides DC bias for the non-inverting input.
b
, R
L
and R
t
are tied to V
cm
for minimum power
R
Channel 2 not shown.
V
cm
Select R
t
to yield desired R
in
= R
t
||R
g
, where R
g
= 1k
.
1
7
6
8
5
3
4
2
1k
+
-
+
-
1k
1k
1k
CLC5612
V
o
R
L
V
cm
0.1
μ
F
6.8
μ
F
+
V
in
R
t
V
cm
V
CC
R
t
and R
L
are tied to V
cm
for minimum power
Note:
Channel 2 not shown.
1
7
6
8
5
3
4
2
1k
+
-
+
-
1k
1k
1k
CLC5612
V
o
R
L
V
cm
0.1
μ
F
6.8
μ
F
+
V
in
R
t
V
cm
V
CC
Note:
R
, R
and R
are tied to V
for minimum power
consumption and maximum output swing.
Channel 2 not shown.
V
cm
1
7
6
8
5
3
4
2
1k
+
-
+
-
1k
1k
1k
CLC5612
0.1
μ
F
6.8
μ
F
+
V
in
R
R
V
CC
V
CC
C
C
V
Low frequency cutoff
where Rg = 1k
.
V
2.5
1
2 R C
π
g
C
=
+
=
,
V
o
Note:
Channel 2 not shown.
1
7
6
8
5
3
4
2
1k
+
-
+
-
1k
1k
1k
CLC5612
0.1
μ
F
6.8
μ
F
+
V
in
R
R
V
CC
V
CC
C
C
V
o
Note:
Channel 2 not shown.
V
Low frequency cutoff
V
2.5
1
2 R C
R
source
whereR
R
2
R
o
C
in
=
+
=
=
>>
,
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相關代理商/技術參數(shù) |
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