參數(shù)資料
型號(hào): CLC5526PCASM
廠商: National Semiconductor Corporation
英文描述: Digital Variable Gain Amplifier (DVGA)
中文描述: 數(shù)字可變?cè)鲆娣糯笃鳎―VGA)
文件頁(yè)數(shù): 8/10頁(yè)
文件大?。?/td> 274K
代理商: CLC5526PCASM
Applications
(Continued)
any stray parasitic impedance into a resonant circuit. By tun-
ing the resonant load, full gain can be achieved with a given
resistive load.
A typical tuned load is shown below in Figure 3 where the
resonant frequency is tuned about 150 MHz.
The 1000
load in this circuit can represent the input imped-
ance of the CLC5956 Analog to Digital converter. Actual val-
ues for the reactive components may vary slightly to account
for board and device parasitic elements.
Typical Application
Although the CLC5526 can be used as a general purpose
digital variable gain amplifier, it was specifically designed to
provide the variable gain function in National’s Diversity Re-
ceiver Chipset. In this application, the CLC5526 drives a
tuned BPF and the CLC5956 Analog to Digital converter.
Digitized IF data is downsampled and tuned with the
CLC5902 dual digital tuner which also provides the AGC
control function. AGC data is fed back to the CLC5526. The
CLC5956 differential input impedance is 1000
, so with the
tuned load, full gain of the CLC5526 is achieved. Figure 4
shows the block diagram of the Diversity Receiver Chipset
application. Figure 5shows the SINAD vs Input Power of the
diversity receiver chipset. For input power levels ranging
from 0 dB to 110 dB, the chip set provides a signal to noise
ratio in excess of the 9 dB required for a typical GSM system.
Layout Considerations
A proper printed circuit layout is essential for achieving high
frequency performance. National Semiconductor provides
evaluation boards for the CLC5526, which include input and
output transformers for impedance matching and single to
differential signal conversion.
Supply bypassing is required for best performance. Provide
a 6.8 μF Tantalum and 0.1 μF ceramic capacitor as close as
possible to the supply pin.
In addition, a 100 pF ceramic capacitor should be placed be-
tween the COMP pin (pin 9) and the system ground. This will
filter high frequency noise from the common-mode level.
Ceramic coupling capacitors should be used to AC couple
both the input and output.Actual values will depend upon the
signal frequency.
DS015016-19
FIGURE 3. CLC5526 Driving a Tuned Load
DS015016-20
FIGURE 4. Diversity Receiver Chipset Block Diagram
DS015016-21
FIGURE 5. Diversity Receiver Chipset
SINAD vs Input Power
www.national.com
8
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