參數(shù)資料
型號: CLC5526
廠商: National Semiconductor Corporation
英文描述: Digital Variable Gain Amplifier (DVGA)
中文描述: 數(shù)字可變增益放大器(DVGA)
文件頁數(shù): 7/10頁
文件大?。?/td> 274K
代理商: CLC5526
Applications
DESCRIPTION
The CLC5526 is a digitally programmable, variable gain am-
plifier with the following features:
8 gain settings ranging from 12 to +30 dB in 6 dB steps
Differential inputs and outputs (externally AC coupled)
Self biased input common-mode voltage
3-bit parallel digital control
Single +5V supply
Low-Power standby mode
Please refer to Figure 1 for a representative block diagram.
GAIN SELECTION
Gain levels can be decreased from the maximum value in 6
dB steps via the 3-bit digital inputs. Table 1 shows the gain
selection truth table for a 1000
differential load.
TABLE 1. Gain Selection Truth Table
Gain Word
0
1
2
3
4
5
6
7
MSB
0
0
0
0
1
1
1
1
ISB
0
0
1
1
0
0
1
1
LSB
0
1
0
1
0
1
0
1
Gain (dB)
12
6
0
+6
+12
+18
+24
+30
Gain settings can be calculated as follows:
GAIN = 12 dB + (Gain Word)
*
6.02 dB
Gain selection has two modes: Transparent or latched, de-
pending on the LATCH input. If the LATCH input is held
LOW, then the device is in the transparent mode. Changes
on data inputs will result in direct changes to the gain setting.
Input data will be latched upon the LOW to HIGH transition of
LATCH. While LATCH is HIGH, digital data will be ignored
until LATCH is strobed low again.
Note:
Upon power-up the analog inputs are disconnected
from the internal amplifier. LATCH will need to be strobed
LOW before an analog output will be present!
DIFFERENTIAL I/O CONSIDERATIONS
Analog inputs and outputs need to be AC coupled to prevent
DC loading of the common-mode voltages. If driving the
CLC5526 from a single-ended 50
source is required, a 1:2
transformer should be used to generate the differential in-
puts. As the differential input impedance of the CLC5526 is
200
, the 1:4 impedance ratio will allow for optimum match-
ing to the 50
source. The secondary outputs of the trans-
former should be AC coupled to the CLC5526 analog inputs,
while the secondary center tap of the transformer should be
directly connected to the system ground.
The CLC5526 is designed to drive differential circuits, such
as the CLC5956 Analog to Digital convertor. Figure 2 below
shows a typical application of the CLC5526.
DRIVING LOADS
Actual gain of the CLC5526 will vary with the output load.
The device is designed to provide +30 dB maximum gain
with a 1000
differential load.
Each output of the CLC5526 contains an internal 300
re-
sistor to the V
rail. Actual gain calculations need to take
this in account with a given external load resistor. The effec-
tive load resistance can be used with the following equation
to calculate max gain values.
A
V
= 20 log (0.0843
*
R
leff
)
Where: R
leff
= R
int
|| R
ext(diff)
R
int
= 600
differential
Chart 1 below shows maximum gain values over output load.
Resistor values are for differential loads.
Stray capacitance at the output, along with the output load
value will form a pole, which can degrade the CLC5526
bandwidth. For a narrow-band application this problem can
be alleviated by using a tuned load, which will incorporate
DS015016-16
FIGURE 1. CLC5526 Block Diagram
DS015016-17
FIGURE 2. Differential I/O Connections
DS015016-18
Chart 1: Maximum Gain vs R
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