參數(shù)資料
型號: CLC532
廠商: National Semiconductor Corporation
英文描述: High-Speed 2:1 Analog Multiplexer(高速2選1模擬多路器)
中文描述: 高速2:1模擬多路復(fù)用器(高速2選1模擬多路器)
文件頁數(shù): 3/12頁
文件大?。?/td> 277K
代理商: CLC532
Recommended Operating Conditions
Absolute Maximum Ratings
3
positive supply voltage (+V
CC
)
negative supply voltage (-V
)
differential voltage between any two GND’s
analog input voltage range
digital input voltage range
output short circuit duration (output shorted to GND)
junction temperature
operating temperature range
CLC532AJP/AJE/AIB
storage temperature range
lead solder duration (+300
°
C)
ESD rating
transistor count
-0.5V to +7.0V
+0.5V to -7.0V
200mV
-V
EE
to +V
CC
-V
EE
to +V
CC
Infinite
+150
°
C
-40
°
C to +85
°
C
-65
°
C to +150
°
C
10 sec
<500V
74
positive supply voltage (+V
CC
)
negative supply voltage (-V
)
differential voltage between any two GND’s
analog input voltage range
SELECT input voltage range (TTL mode)
SELECT input voltage range (ECL mode)
C
COMP
range
2
+5V
-5.2V or -5.0V
10mV
±2V
0.0V to +3.0V
-2.0V to 0.0V
0pF to 100pF
thermal data
14-pin plastic
14-pin Cerdip
14-pin SOIC
20-terminal LCC
θ
JC
(°C/W)
55
35
35
35
θ
(°C/W)
100
85
105
50
Note 1:
Test levels are as follows:
AJ : 100% tested at +25°C.
*
Note 2: The CLC532 does not require external C
COMP
capacitors for proper
operation.
Note 3: Absolute maximum ratings are limiting values, to be applied individually,
and beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
maximum ratings for extended periods may affect device reliability.
System Timing Diagram
Switching Transient Timing Diagram
A
SELECT
B
ST
2ns
~
OUTPUT
Channel A = 0V
Channel B = 0V
A
SELECT
B
SWT90
SWT10
90%
10%
TSx
TRx
TRx
SETTLING ERROR
WINDOW
CHANNEL A = +1V
CHANNEL B = -1V
OS
... where TSx is TS14 or TSP or TSS,
and TRx is TRS ro TSL.
OUTPUT
3
http://www.national.com
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