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參數(shù)資料
| 型號(hào)： | CLC453ALC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Comlinear CLC453 Single Supply, Low-Power, High Output, Programmable Buffer |
| 中文描述： | BUFFER AMPLIFIER, UUC5 |
| 封裝： | DIE |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 330K |
| 代理商： | CLC453ALC |
http://www.national.com
10
Figure 11: Power Derating Curve
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. Comlinear provides
evaluation boards for the CLC453 (CLC730013-DIP,
CLC730027-SOIC, CLC730068-SOT) and suggests their
use as a guide for high frequency layout and as an aid for
device testing and characterization.
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
I
Include 6.8
μ
F tantalum and 0.1
μ
F ceramic
capacitors on both supplies.
I
Place the 6.8
μ
F capacitors within 0.75 inches
of the power pins.
I
Place the 0.1
μ
F capacitors less than 0.1 inches
from the power pins.
I
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
I
Minimize all trace lengths to reduce series
inductances.
I
Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.
Evaluation Board Information
Data sheets are available for the CLC730013/
CLC730027 and CLC730068 evaluation boards. The
evaluation board data sheets provide:
I
Evaluation board schematics
I
Evaluation board layouts
I
General information about the boards
The CLC730013/CLC730027 data sheet also contains
tables of recommended components to evaluate several
of Comlinear’s high speed amplifiers. This table for the
CLC453 is illustrated below. Refer to the evaluation
board data sheet for schematics and further information.
Components Needed to Evaluate the
CLC453 on the Evaluation Board:
I
R
in
, R
out
- Typically 50
(Refer to the
Basic
Operation
section of the evaluation board data
sheet for details)
I
R
t
- Optional resistor for inverting gain configura-
tions (Select R
t
to yield desired input impedance
= R
g
|| R
t
)
I
C
1
, C
2
- 0.1
μ
F ceramic capacitors
I
C
3
, C
4
- 6.8
μ
F tantalum capacitors
Components not used:
I
C
5
, C
6
, C
7
, C
8
I
R
1
thru R
8
The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation. For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.
Special Evaluation Board
Considerations for the CLC453
To optimize off-isolation of the CLC453, cut the R
f
trace on
both the CLC730013 and the CLC730027 evaluation
boards. This cut minimizes capacitive feedthrough
between the input and the output. Figure 12 shows where
to cut both evaluation boards for improved off-isolation.
Figure 12: Evaluation Board Changes
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for
Comlinear’s monolithic amplifiers that:
I
Support Berkeley SPICE 2G and its many derivatives
I
Reproduce typical DC, AC, Transient, and Noise
performance
I
Support room temperature simulations
The
readme
file that accompanies the diskette lists
released models, and provides a list of modeled parame-
ters. The application note OA-18, Simulation SPICE
Models for Comlinear’s Op Amps, contains schematics
and a reproduction of the readme file.
Single Supply Cable Driver
The typical application shown on the front page shows
the CLC453 driving 10m of 75
coaxial cable. The
CLC453 is set for a gain of +2V/V to compensate for the
divide-by-two voltage drop at V
o
.
Application Circuits
730013
REV C
Cut trace here
407 Fig4 (Left)
R
R
R
R
R8
R5
C
R
R
C
R
OUT
C6
C2
C1
C5
C8
IN
R
R
RF
C7
-V
cc
+V
cc
GND
A Na ti on a l Semi con du ctor C ompa n y
(303) 226-0500
+
+
407 Fig 3 (Right)
Cut trace here
P
Ambient Temperature (
°
C)
0
0.2
0.4
0.6
0.8
1.0
-40 -20
0
20
40
60
80 100 120
180
AJP
AJE
SOT
140 160
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