參數(shù)資料
型號： CLC451AJ
廠商： National Semiconductor Corporation
英文描述： Single Supply, Low-Power, High Output, Programmable Buffer
中文描述： 單電源，低功耗，高輸出，可編程緩沖區(qū)
文件頁數(shù)： 9/12頁
文件大?。?/td> 252K
代理商： CLC451AJ
9
http://www.national.com
Figure 8: Dual Supply, A
v
= +1V/V Configuration
Figure 9: Dual Supply, A
v
= +2V/V Configuration
Bandwidth vs. Output Amplitude
The bandwidth of the CLC451 is at a maximum for
output voltages near 1V
pp
. The bandwidth decreases
for smaller and larger output amplitudes. Refer to the
Frequency Response vs.V
o
plots.
Load Termination
The CLC451 can source and sink near equal amounts of
current. For optimum performance, the load should be
tied to V
cm
.
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC451 will
improve stability and settling performance.
Frequency Response vs. C
L
and
Recommended R
s
vs. C
L
plots, in the typical performance section, give the
recommended series resistance value for optimum
flatness at various capacitive loads.
The
Transmission Line Matching
One method for matching the characteristic impedance
(Z
o
) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
Figure 10 shows typical inverting and non-inverting
circuit configurations for matching transmission lines.
Non-inverting gain applications:
I
Connect pin 2 as indicated in the table in the
Closed Loop Gain Selection
section.
I
Make R
1
, R
2
, R
6
, and R
7
equal to Z
o
.
I
Use R
3
to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.
Inverting gain applications:
I
Connect R
3
directly to ground.
I
Make the resistors R
4
, R
6
, and R
7
equal to Z
o
.
I
Make R
5
II R
g
= Z
o
.
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C
6
to match the output transmission line over a
greater frequency range. C
6
compensates for the increase
of the amplifier’s output impedance with frequency.
Figure 10:Transmission Line Matching
Power Dissipation
Follow these steps to determine the power consumption
of the CLC451:
1. Calculate the quiescent (no-load) power:
P
amp
= I
CC
(V
CC
- V
EE
)
2. Calculate the RMS power at the output stage:
P
o
= (V
CC
- V
load
) (I
load
), where V
load
and I
load
are the RMS voltage and current across the
external load.
3. Calculate the total RMS power:
P
t
= P
amp
+ P
o
The maximum power that the DIP, SOIC, and SOT
packages can dissipate at a given temperature is
illustrated in Figure 11. The power derating curve for
any CLC451 package can be derived by utilizing the
following equation:
where
T
amb
= Ambient temperature (°C)
θ
JA
= Thermal resistance, from junction to ambient,
for a given package (°C/W)
(175
T
amb
JA
°
θ
)
0.1
μ
F
6.8
μ
F
+
V
o
V
in
R
t
V
CC
1
CLC451
7
6
8
5
3
4
2
1k
1k
0.1
μ
F
6.8
μ
F
+
V
EE
0.1
μ
F
6.8
μ
F
+
V
o
V
in
R
t
V
CC
1
CLC451
7
6
8
5
3
4
2
1k
1k
0.1
μ
F
6.8
μ
F
+
V
EE
Z
0
R
6
V
o
Z
0
R
4
R
5
+
R
3
Z
0
R
1
R
2
V
1
V
2
+
C
6
R
7
1
CLC451
7
6
8
5
3
4
2
1k
1k
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