參數(shù)資料
型號(hào): CLC436AJ
廠商: National Semiconductor Corporation
英文描述: 200MHz, 【15V, Low-Power Voltage Feedback Op Amp
中文描述: 200MHz的,【15V的,低功耗,電壓反饋運(yùn)算放大器
文件頁(yè)數(shù): 5/6頁(yè)
文件大?。?/td> 119K
代理商: CLC436AJ
Figure 3: Single Supply Circuit
Power Dissipation
The power dissipation of an amplifier can be described
in two conditions:
Quiescent Power Dissipation - P
Q
(No Load Condition)
Total Power Dissipation - P
T
(with Load Condition)
The following steps can be taken to determine the
power consumption of the CLC436:
1. Determine the quiescent power
P
Q
= I
cc
(V
cc
- V
ee
)
2. Determine the RMS power at the output stage
P
O
= (V
cc
- V
load
) (I
load
)
3. Determine the total RMS power
P
T
= P
Q
+ P
O
The maximum power that the package can dissipate at
a given temperature is illustrated in the
Power Derating
plot in the
Typical Performance Characteristics
section. The power derating curve for any package
can be derived by utilizing the following equation:
(
θ
where: T
amb
= Ambient temperature in °C
θ
JA
= Thermal resistance, from junction to
ambient, for a given package in °C/W
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. Comlinear provides eval-
uation boards for the CLC436 (730013 - DIP, 730027-
SOIC) and suggests their use as a guide for high
frequency layout and as an aid for device testing and
characterization.
Supply bypassing is required for optimum performance.
The bypass capacitors provide a low impedance
current return path at the supply pins. They also provide
high frequency filtering on the power supply traces.
Other layout factors also play a major role in high
frequency performance. The following steps are
recommended as a basis for high frequency layout:
1. Include 6.8
μ
F tantalum and 0.01
μ
F ceramic
bypass capacitors on both supplies.
2. Place the 6.8
μ
F capacitors within 0.75 inches
of the power pins.
3. Place the 0.01
μ
F capacitors within 0.1 inches
of the power pins.
4. Remove the ground plane near the input and
output pins to reduce parasitic capacitance.
5. Minimize all trace lengths to reduce series
inductances.
State Variable Filter
The filter shown on the front page offers both a band-
pass and a low pass output. The design equations are
shown below.
The state variable filter can be modified to obtain a
tunable band pass filter. This technique is shown in
the CLC522, Wideband Variable Gain Amplifier,
data sheet.
Transimpedance Application
The low 1.1pA/
Hz input current noise and unity gain
stability make the CLC436 useful as a photo diode pre-
amplifier. Figure 4 illustrates a transimpedance amplifier.
R
f
sets the transimpedance gain. The photodiode current
is multiplied by R
f
to determine the output voltage.
Figure 4: Transimpedance Amplifier
The feedback capacitor (C
f
) is required to compensate
for the added input capacitance of the photodiode (C
d
).
The feedback capacitance reduces peaking in the fre-
quency response. As the value of the feedback capac-
itance increases from zero, the rolloff of the response
will increase.
P
175
T
amb
JA
=
°
)
Q
R
R
A
R
R
,desired mid band gain
f
Q
2 R C,desired resonant frequency
R
3
=
R
1
3
v
1
4
r
2
=
=
=
+
CLC436
-
R
f
V
o
V
in
V
cc
R
g
C
2
R
2
R
1
V
cc
C
1
Applications Circuit
I
in
-
+
CLC436
C
d
R
f
C
f
Photo Diode
Representation
V
o
= I
in
*R
f
V
o
5
http://www.national.com
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