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參數(shù)資料
| 型號(hào)： | CLC431 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual Wideband Monolithic Op Amp with Disable |
| 中文描述： | 雙寬帶單片運(yùn)算放大器具有禁用 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 863K |
| 代理商： | CLC431 |
Fig. 2 illustrates the differential mode of the CLC431's
disable feature for ECL-type logic. In order for this mode
to operate properly,
V
RTTL
must be left floating while
DIS
and
DIS
are to be connected directly to the ECL gate as
illustrated. Applying a differential logic "high" (
DIS
-
DIS
≥
0.4Volts) switches the tail current of the differential pair
from Q2 to Q1 and results in the disablingof that CLC431
channel. Alternatively, applying a differential logic "low"
(
DIS
-
DIS
≤
-0.4Volts) switches the tail current of the
differential pair from Q1 to Q2 and results in the enabling
of that same channel. The internal clamp, mentioned
above, also protects against excessive differential volt-
ages up to 30Volts while limiting input currents to <3mA.
DC Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot
be cancelled and each contributes to the total DC offset
voltage at the output by the following equation:
The input resistor R
s
is that resistance seen when looking
from the non-inverting input back towards the source. For
inverting DC-offset calculations, the source resistance
seen by the input resistor R
g
must be included in the
output offset calculation as a part of the non-inverting
gain equation. Application note OA-7 gives several circuits
for DC offset correction.
Layout Considerations
It is recommended that the decoupling capacitors (0.1
μ
F
ceramic and 6.8
μ
F electrolytic) should be placed as close
as possible to the power supply pins to insure a proper
high-frequency low impedance bypass. Careful attention
to circuit board layout is also necessary for best
performance. Of particular importance is the control of
parasitic capacitances (to ground) at the output and
invering input pins. See CLC431/432 Evaluation Board
literature for more information.
Applications Circuits
2:1 Video Mux (CLC431)
Fig. 3 illustrates the connections necessary to configure
the CLC431 as a 2:1 multiplexer in a 75
system. Each
of the two CLC431's amplifiers is configured with a non-
inverting gain of +2V/V using 634
feedback (R
f
) and
gain-setting (R
g
) resistors. The feedback resistor value is
lower than that recommended in order to compensate for
the reduction of loop-gain that results from the inclusion
of the 50
resistor (R
i
) in the feedback loop. This 50
resistor serves to isolate the output of the active channel
from the impedance of the inactive channel yet does not
affect the low output impedance of the active channel.
Notice that for proper operation
V
RTTL
1
(pin 13) is grounded
and
V
RTTL
2
(pin 9) is unconnected. The pins associated
with the disable feature are to be connected as follows:
DIS1
and
DIS2
(pins 3 & 10) are connected together as
well as
DIS2
and
DIS1
(pins 5 & 12). Channel 1 is
selected with the application of a logic "low" to SELECT
while a logic "high" selects Channel 2.
front page). Also note that both amplifiers are guaranteed
to be enabled if all three of these pins are unconnected.
Fig. 1 illustrates the single-ended mode of the CLC431's
disable feature for logic families such as TTL and CMOS.
In order to operate properly,
V
RTTL
must be grounded,
thereby biasing
DIS
to approximately +1.4V through the
two internal series diodes. For single-ended operation,
DIS
should be left floating. Applying a TTL or CMOS logic
"high" (i.e. >2.0Volts) to
DIS
will switch the tail current of
the differential pair to Q1 and "shut down" Q2 which
results in the disablingof that channel of the CLC431.
Alternatively, applying a logic "low" (i.e. <0.8Volts) to
DIS
will switch the tail current from Q1 to Q2 effectively
enablingthat channel. If
DIS
is left floating under single-
ended operation, then the associated amplifier is guaran-
teed to be disabled
The disable feature of the CLC431 is such that
DIS
and
DIS
have common-mode input voltage ranges of (+V
CC
)
to (-V
CC
+3V) and are so guaranteed over the commercial
temperature range. Internal clamps (not shown) protect
the
DIS
input from excessive input voltages that could
otherwise cause damage to the device. This condition
occurs when enough source current flows into the node
so as to allow
DIS
to rise to V
CC
. This clamp is activated
once
DIS
exceeds
DIS
by 1.5Volts and guarantees that
V
DIS
(ground referenced) does not exceed 4.7Volts.
V
RTTL
+V
CC
+V
CC
+V
CC
DIS
DIS
V
non-inv
V
inv
V
out
CLC431
100k
100k
Q
1
Q
2
TTL
CMOS
+
-
Fig. 1
V
I
R
R
R
V
R
R
I
R
offset
bn
s
f
g
io
f
g
bi
f
= ±
+
+
+
+
1
1
5
http://www.national.com
V
RTTL
+V
CC
+V
CC
+V
CC
DIS
DIS
100k
100k
Q
1
Q
2
ECL
510
-5V
-5V
510
V
non-inv
V
inv
V
out
CLC431
+
-
Fig. 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC431A/BCA | 制造商:Rochester Electronics LLC 功能描述: |
| CLC431A8B | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Current-Feedback Operational Amplifier |
| CLC431AE-QML | 制造商:Rochester Electronics LLC 功能描述:DUAL WIDEBAND OP AMP - Bulk |
| CLC431AJ-QML | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| CLC432 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Dual Wideband Monolithic Op Amp with Disable |
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