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6
The maximum power that the package can dissipate at a
given temperature is illustrated in the
Power Derating
curves in the
Typical Performance
section. The power
derating curve for any package can be derived by
utilizing the following equation:
where: T
amb
= Ambient temperature (°C)
θ
JA
= Thermal resistance, from junction to
ambient, for a given package (°C/W)
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. Comlinear provides evalu-
ation boards for the CLC427 (730038 - DIP, 730036-
SOIC) and suggests their use as a guide for high
frequency layout and as an aid for device testing and
characterization.
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
1. Include 6.8
μ
F tantalum and 0.1
μ
F ceramic
capacitors on both supplies.
2. Place the 6.8
μ
F capacitors within 0.75 inches
of the power pins.
3. Place the 0.1
μ
F capacitors within 0.1 inches
of the power pins.
4. Remove the ground plane under and around
the part, especially near the input and output
pins to reduce parasitic capacitance.
5. Minimize all trace lengths to reduce series
inductances.
Additional information is included in the evaluation board
literature.
Typical Application Circuit
The typical application shown on the front page illustrates
the near rail-to-rail performance of the CLC427.
Multiple Feedback Bandpass Filter
Figure 9 illustrates a bandpass filter and design
equations. The circuit operates from a single supply of
+5V. The voltage divider biases the non-inverting input to
2.5V. The input is AC coupled to prevent the need for
level shifting the input signal at the source. Use the
design equations to determine R
1
and R
2
based on the
desired Q and center frequency.
This example illustrates a bandpass filter with Q = 4 and
center frequency f
c
= 1MHz. Figure 10 indicates the
filter response.
Figure 9: Bandpass Filter Topology
Figure 10: Bandpass Response
Distribution Amplifier
Figure 11 illustrates a distribution amplifier. The topology
utilizes the dual amplifier package. The input is
AC coupled and the non-inverting terminals of both
amplifiers are biased at 2.5V.
Figure 11: Distribution Amplifier
175
(
T
amb
JA
°
θ
)
Applications Circuits
M
Frequency (MHz)
40
30
20
-10
1
10
10
0
30.6dB
940kHz
+
-
1/2
CLC427
R
2
3.16k
0.1
μ
F
6.8
μ
F
+
V
o
V
in
+5V
5.1k
C
3(5)
2(6)
4
8
1(7)
5.1k
C
390pF
390pF
R
1
50
R
Q
f c
R
4Q
f
resonant frequency
R
A
2Q
A
mid band gain
2
r
r
1
2
2
2
=
=
=
=
=
π
+
-
C1/2
R
f
0.1
μ
F
6.8
μ
F
+
V
o1
V
in
+5V
R
g
C
R
3(5)
2(6)
8
1(7)
C
C
R
R
o
R
o
R
o
Z
o
+
-
C1/2
R
f
V
o2
R
g
C
3(5)
2(6)
4
1(7)
R
o
R
o
Z
o