參數(shù)資料
型號(hào): CLC426
廠商: National Semiconductor Corporation
英文描述: Wideband, Low-Noise, Voltage Feedback Op Amp
中文描述: 寬帶,低噪聲,電壓反饋運(yùn)算放大器
文件頁數(shù): 6/8頁
文件大?。?/td> 1005K
代理商: CLC426
Single-Supply Operation
The CLC426 can be operated with single power supply as
shown in fig. 7. Both the input and output are capacitively
coupled to set the dc operating point.
DAC Output Buffer
The CLC426's quick settling, wide bandwidth and low
differential input capacitance combine to form an excel-
lent I-to-V converter for current-output DACs in such
applications as reconstruction video. The circuit of fig. 8
implements a low-noise transimpedance amplifier com-
monly used to buffer high-speed current output devices.
The transimpedance gain is set by R
f
. A feedback
capacitor, C
f
, is needed in order to compensate for the
inductive behavior of the closed-loop frequency response
of this type of circuit. Equation 3 shows a means of
calculating the value of C
f
which will provide conditions for
a maximally-flat signal frequency response with approxi-
mately 65° phase margin and 5% step-response over-
shoot. Notice that C
t
is the sum of the DAC output
capacitance and the differential input capacitance of the
CLC426 which is located in its Electrical Characteristics
Table. Notice also that CLC426's gain-bandwidth product
(GBW) is also located in the same table. Equation 5
provides the resulting signal bandwidth.
C
C
R GBW
2
π
+
f
t
=
2
Eq. 3
C
C
C
t
out
in dif
=
Eq. 4
signalbandwidth
GBW
2
π
R C
t
=
1
2
Eq. 5
Sallen-Key Active Filters
The CLC426 is well suited for Sallen-Key type of active
filters. Fig. 9 shows the 2
nd
order Sallen-Key band-pass
filter topology and design equations.
Fig. 9
To design the band-pass, begin by choosing values for R
f
and R
g
, for example
R
R
f
g
=
sonable values for C
1
and C
2
(where C
1
=5C
2
) and then
compute R
1
. R
2
and R
3
can then be computed. For
optimum high-frequency performance it is recommended
that the resistor values fall in the range of 10
to 1k
and
the capacitors be kept above 10pF. The design can
be further improved by compensating for the delay through
the op amp. For further details on this technique, please
request Application Note OA-21 from National Semicon-
ductor Corporation.
=
200
. Then choose rea-
Printed Circuit Board Layout
Generally, a good high-frequency layout will keep power
supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes
to ground will cause frequency-response peaking and
possible circuit oscillation, see OA-15 for more information.
National suggests the CLC730013 (through-hole) or the
CLC730027 (SOIC) evaluation board as a guide for high-
frequency layout and as an aid in device testing and
characterization.
Fig. 7
Fig. 8
C
C
G
R
R
desiredmid
band gain
R
Q
(
GC
f
where f
desiredcenter frequency
R
GR
Q
G
G
Q
G
G
R
GR
Q
G
G
G
Q
f
g
2
1
1
1
2
1
2
2
2
2
3
1
2
2
2
1
5
1
2
2
1 4 8
2
1
4 8
.
2
5
1 4 8
2
1
4
=
= +
=
)
=
=
+
+
+
=
+
+
,
,
.
.
π
http://www.national.com
6
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