參數(shù)資料
型號: CLC425ALC
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運(yùn)動控制電子
英文描述: Faceplate; Enclosure Color:Off White RoHS Compliant: Yes
中文描述: OP-AMP, 800 uV OFFSET-MAX, 1900 MHz BAND WIDTH, UUC
封裝: DIE
文件頁數(shù): 8/9頁
文件大?。?/td> 1275K
代理商: CLC425ALC
20
200
600
50
50
40k
50k
180
20
10
P
i
MiT16-6T
P
o
A
v
=+10
A
v
=-3
806
50
1:4
CLC425
CLC404
0.1
μ
F
1pF
Gain =P
o
P
i
= 35.6dB
Figure 14: Very Low Noise Figure Amplifier
R
f=
1k
R
1=
45.3
R
=
681
R
g=
50
R
2=
200
V
o
V
in
CLC425
L
=
0.1
μ
H
C
=
470pF
C
1=
2200pF
V
V
sC R
sC R
R
R
+
R
R
sLR
s LCR R
sL R
R
R R
o
in
o
f
f
g
g
g
g
g
K
=
+
+
)
+
+
+
)
+
1
1
2
1
1
V
V
K
sR C
K
R
R
o
in
o
o
f
g
= +
1
;
R
R
R
R
R
R
R
b
a
f
g
a
||
,
>>
R
f
R
b
R
a
R
g
V
o
V
in
CLC425
R
C
50
50
R
f
R
g
CLC425
R
1
R
2
C
2
C
1
Figure 17: Low Noise Magnetic Media Equalizer
K
R
R
o
f
g
= +
1
R
f
R
b
R
g
CLC425
V
in
V
out
C
f
Figure 18: Equalizer Frequency Response
Low-Noise Phase-Locked Loop Filter
The CLC425 is extremely useful as a Phase-Locked
Loop filter in such applications as frequency synthesiz-
ers and data synchronizers. The circuit of Figure 19
implements one possible PLL filter with the CLC425.
Figure 19: Phased-Locked Loop Filter
Decreasing the Input Noise Voltage
The input noise voltage of the CLC425 can be reduced
from its already low 1.05nV/
Hz by slightly increasing the
supply current. Using a 50k
resistor to ground on pin 8,
as shown in the circuit of Figure 14, will increase the
quiescent current to
17mA and reduce the input noise
voltage to < 0.95nV/
Hz.
Printed Circuit Board Layout
Generally, a good high-frequency layout will keep power
supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes
to ground will cause frequency response peaking and
possible circuit oscillation, see OA-15 for more informa-
tion. National suggests the CLC730013-DIP,
CLC730027-SOIC, or CLC730068-SOT evaluation
board as a guide for high-frequency layout and as an aid
in device testing and characterization.
Low Noise Integrator
The CLC425 implements a deBoo integrator shown in
Figure 15. Integration linearity is maintained through
positive feedback. The CLC425's low input offset
voltage and matched inputs allowing bias current
cancellation provide for very precise integration. Stabil-
ity is maintained through the constraint on the circuit
elements.
Figure 15: Low Noise Integrator
High-Gain Sallen-Key Active Filters
The CLC425 is well suited for high-gain Sallen-Key type
of active filters. Figure 16 shows the 2
nd
order Sallen-Key
low pass filter topology. Using component predistortion
methods as discussed in OA-21 enables the proper
selection of components for these high-frequency filters.
Figure 16: Sallen-Key Active Filter Topology
Low Noise Magnetic Media Equalizer
The CLC425 implements a high-performance low-noise
equalizer for such applications as magnetic tape
channels as shown in Figure 17. The circuit combines an
integrator with a bandpass filter to produce the low-
noise equalization. The circuit's simulated frequency
response is illustrated in Figure 18.
http://www.national.com
8
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