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參數(shù)資料
| 型號(hào)： | CLC418AJ |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual High-Speed, Low-Power Line Driver |
| 中文描述： | 雙高速，低功耗，線路驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 280K |
| 代理商： | CLC418AJ |
7
http://www.national.com
following equation:
SR
>
5
f
V
peak
where V
peak
is the peak output sinusoidal voltage.
The slew rate of the CLC418 in inverting gains is always
higher than in non-inverting gains.
AC Design (linear phase/constant group delay)
The recommended value of R
f
produces minimal peaking
and a reasonably linear phase response. To improve
phase linearity when |A
v
| < 6, increase R
f
approximately
50% over its recommended value. Some adjustment of
R
f
may be needed to achieve phase linearity for your
application. See the
AC Design (small signal band-
width)
sub-section for other effects of changing R
f
.
Propagation delay is approximately equal to group delay.
Group delay is related to phase by this equation:
where
φ
(f) is the phase in degrees. Linear phase implies
constant group delay. The technique for achieving linear
phase also produces a constant group delay.
AC Design (peaking)
Peaking is sometimes observed with the recommended
R
f
. If a small increase in R
f
does not solve the problem,
then investigate the possible causes and remedies
listed below:
I
Capacitance across R
f
I
Do not place a capacitor across
R
f
I
Use a resistor with low parasitic
capacitance for R
f
I
A capacitive load
I
Use a series resistor between the output
and a capacitive load (see the
Settling
Time versus C
L
plot)
I
Long traces and/or lead lengths between R
f
and the CLC418
I
Keep these traces as short as possible
For non-inverting and transimpedance gain configurations:
I
Extra capacitance between the inverting
pin and ground (C
g
)
I
See the
Printed Circuit Board Layout
sub-section below for suggestions on
reducing C
g
I
Increase R
f
if peaking is still observed
after reducing C
g
For inverting gain configurations:
I
Inadequate ground plane at the non-inverting
pin and/or long traces between non-inverting
pin and ground
I
Place a 50 to 200
resistor between the
non-inverting pin and ground (see R
t
in
Figure 2)
AC Design (crosstalk)
Crosstalk performance depends on the layout. Three
layout techniques that can reduce crosstalk are:
I
Provide short symmetrical ground return paths for:
I
the inputs
I
the supply bypass capacitors
I
the load
I
Provide a short, grounded guard trace that:
I
goes underneath the package
I
is 0.1” (3mm) from the package pins
I
is on top and bottom of the printed circuit
board with connecting vias
I
Try different bypass capacitors to reduce high
frequency crosstalk
The CLC418’s evaluation board was used to produce the
Input-Referred Crosstalk
plot.
Capacitive Loads
Capacitive loads, such as found in A/D converters,
require a series resistor (R
s
) in the output to improve
settling performance. The
Settling Time vs. Capacitive
Load
plot in the
Typical Performance Characteristics
section provides the information for selecting this resistor.
Using a resistor in series with a reactive load will also
reduce the load’s effect on amplifier loop dynamics. For
instance, driving coaxial cables without an output series
resistor may cause peaking or oscillation.
Transmission Line Matching
One method for matching the characteristic impedance
of a transmission line is to place the appropriate
resistor at the input or output of the amplifier. Figure 6
shows the typical circuit configurations for matching
transmission lines.
Figure 6: Transmission Line Matching
In non-inverting gain applications, R
g
is connected
directly to ground. The resistors R
1
, R
2
, R
6
, and R
7
are
equal to the characteristic impedance, Z
o
, of the
transmission line or cable. Use R
3
to isolate the
amplifier from reactive loading caused by the transmis-
sion line, or by parasitics.
In inverting gain applications, R
3
is connected directly to
ground. The resistors R
4
, R
6
, and R
7
are equal to Z
o
. The
parallel combination of R
5
and R
g
is also equal to Z
o
.
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C
6
to match the output transmission line over a greater
frequency range. It compensates for the increase of
the op amps output impedance with frequency.
τ
φ
d
φ
gd
d
f
1
360
f
f
1
360
f
f
( )
=
°
( )
≈
°
( )
+
-
418 Fig6
R
3
Z
0
R
6
V
o
Z
0
R
1
R
2
+
-
R
g
Z
0
R
4
R
5
V
1
V
2
+
-
R
f
C
6
R
7
C1/2
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相關(guān)代理商/技術(shù)參數(shù) |
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| CLC420 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:High-Speed, Voltage Feedback Op Amp |
| CLC420AE-QML | 制造商:Rochester Electronics LLC 功能描述:HI SPEED VOLTAGE FEEDBK OP AMP - Bulk 制造商:Texas Instruments 功能描述: |
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| CLC420AID | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
| CLC420AJE | 制造商:Texas Instruments 功能描述:Operational Amplifier, Single AMP, Bipolar, 8 Pin, Plastic, SOP |
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