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參數(shù)資料
| 型號(hào)： | CLC412 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual Wideband Video Op Amp |
| 中文描述： | 雙寬帶視頻運(yùn)算放大器 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 1398K |
| 代理商： | CLC412 |
bandwidth curves, labeled "BW", correspond to the two
(solid) "R
f
" curves. These results may deviate from that
produced by the analysis of OA-13 since these plots
were produced from an actual board layout that included
parasitic capacitances not accounted for by the analysis
of OA-13. It should be noted that a non-inverting gain of
+1V/V requires an R
f
=1k
and the output voltage used
for both plots is 2V
pp
.
In order to bandlimit the CLC412 at any particular gain
setting, a larger value of R
f
(than previously recommended
in the plots above) is needed. Following the analysis in
OA-13, we find the CLC412’s "optimum feedback
transimpedance", Z
t
*, below.
The "optimum feedback transimpedance" is unique for
each current-feedback op amp and determines the
recommended value of R
f
for a particular gain setting.
Drawing a horizontal line on the “Open-loop
Transimpedance, Z(s)” plot from 57.5dB (on the left
vertical axis), we find the intersection with the
transimpedance magnitude trace occurs at a frequency
of 180MHz. This frequency is only an approximationof
the CLC412’s small-signal bandwidth. From this
intersection, one can see that an increase in Z
t
will
produce a new intersection occurring at a lower frequency.
This is the process to follow when bandlimiting. Once the
target small-signal bandwidth is determined, the new
value of Z
t
is picked off the graph at the point where the
this frequency and the transimpedance magnitude trace
intersect. One can then back track to figure the value of
the feedback resistor, R
f
=Z
t
-R
in
(1+R
f
/R
g
). This new value
of R
f
will produce the desired frequency roll-off.
Circuit Layout
With all high-frequency devices, board layouts with stray
capacitances have a strong influence over AC
performance. The CLC412 is no exception and its input
and output pins are particularly sensitive to the coupling
of parasitic capacitances (to ac ground) arising from
traces or pads placed too closely (<0.1") to power or
ground planes. In some cases, due to the frequency
response peaking caused by these parasitics, a small
adjustment of the feedback resistor value will serve to
compensate the frequency response. Also, it is very
important to keep the parasitic capacitance across the
feedback resistor to an absolute minimum.
The performance plots in the data sheet can be
reproduced using the evaluation boards available from
Comlinear. There are two types of boards; the DIP
(#730038) and SOIC (#730036). The #730036 board
uses all SMT parts for the evaluation of the CLC412 in its
surface mount package. Either of these layouts can
assist the designer in obtaining the desired performance.
In addition, the boards can serve as an example layout
for the final production printed circuit board.
Care must also be taken with the CLC412's layout in
order to achieve the best circuit performance, particularly
channel-to-channel isolation. The decoupling capacitors
(both tantalum and ceramic) must be chosen with good
high frequency characteristics to decouple the power
supplies and the physical placement of the CLC412’s
external components is critical. Grouping each amplifier’s
external components with their own ground connection
and separating them from the external components of
the opposing channel with the maximum possible distance
is recommended. The input (R
in
) and gain-setting resistors
(R
g
) are the most critical. It is also recommended that the
ceramic decoupling capacitor (0.1
μ
F chip or radial-leaded
with low ESR) should be placed as closely to the power
pins as possible.
Package Parasitics
In addition to the parasitic capacitances arising from the
board layout, each of the CLC412's packages has its
own characteristic set of parasitic capacitances and
inductances causing frequency response variation from
package to package as shown in the plot below labeled
"Frequency Response vs. Package Type". Due to its
much smaller size, the CLC412AJE (8-pin SOIC) shows
the least amount of peaking.
Matching Performance
With proper board layout, the AC performance match
between the two CLC412’s amplifiers can be tightly
Z
R
R
R
R
LOG
dB
t
f
in
f
g
=
+
+
=
+
+
=
(
)
=
1
634
60 1
634
634
754
20
754
57 5
.
CLC412
+
CLC412
-
V
in
V
out
634
314
634
25
59
50
50
50
50
634
+
-
Figure 3
http://www.national.com
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC412A8B | Dual Wideband Video Op Amp |
| CLC412AJE | Dual Wideband Video Op Amp |
| CLC412AMC | Dual Wideband Video Op Amp |
| CLC412AIB | Dual Wideband Video Op Amp |
| CLC412A8L-2A | Dual Wideband Video Op Amp |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC412 WAF | 制造商:Texas Instruments 功能描述: |
| CLC412A/B2A | 制造商:Rochester Electronics LLC 功能描述: |
| CLC412A8B | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Wideband Video Op Amp |
| CLC412A8D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current-Feedback Operational Amplifier |
| CLC412A8L-2A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Wideband Video Op Amp |
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