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參數(shù)資料
| 型號(hào)： | CLC409ALC |
| 廠商： | COMLINEAR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Very Wideband, Low Distortion Monolithic Op Amp |
| 中文描述： | OP-AMP, 4500 uV OFFSET-MAX, UUC8 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 329K |
| 代理商： | CLC409ALC |
Application Division
(Continued)
CLC409 does not show an intercept type performance.
(where the relative spurious levels change at a 2X rate vs.
the test tone powers), due to an internal full power bandwidth
enhancement circuit that boosts the performance as the
output swing increases while dissipating negligible quiescent
power under low output power conditions. This feature en-
hances the distortion performance and full power bandwidth
to match that of much higher quiescent supply current parts.
Figure 3
shows a typical application using the CLC409 to
drive an ADC. The series resistor, R
, between the amplifier
output and the ADC input is critical to achieving best system
performance. This load capacitance, if applied directly to the
output pin, can quickly lead to unacceptable levels of ringing
in the pulse response. The plot of R
and settling time vs. C
L
on the previous page is an excellent starting point for setting
R
. The value derived in that plot minimizes the step settling
time into a fixed discrete capacitive load. Several additional
constraints should be considered, however, in driving the
capacitive input or an ADC.
There is an option to increase R
, bandlimiting at the ADC
input for either noise or Nyquist bandlimiting purposes. In-
creasing R
too much, however, can induce an unacceptably
large input glitch due to switching transients coupling
through from the convert signal. Also, C
is oftentimes a
voltage dependent capacitance. This input impedance
non-linearity will induce distortion terms that will increase as
R
is increased. Only slight adjustments up or down from the
recommended R
value should therefore be attempted in
optimizing system performance.
DC Accuracy and Noise
The CLC409 offers an improved offset voltage over the pin
compatible CLC400 low gain amplifier. The offset adjustment
available on the CLC400 was therefore not included in this
part. The Output Offset equation below shows the output
offset computation equation for the non-inverting configura-
tion with an example using the typical bias current and offset
specifications for A
V
= +2.
Output Offset
V
O
=(
±
I
bn
R
in
±
V
io
)(1+R
f
/R
g
)
±
I
bi
R
f
Example Computation for A
V
=+2, R
f
=250
, R
in
=25
:
V
O
=(
±
10μA (25
)
±
0.5mV)2
±
10μA (250
)=
±
3.25mV
This low output offset voltage is a marked improvement over
earlier very high speed amplifiers. Further improvement in
the output offset voltage and drift is possible using the com-
posite amplifiers described in Application Note OA-7.
The two input bias currents are physically unrelated in both
magnitude and polarity for the current feedback topology. It
is not possible, therefore, to cancel their effects by matching
the source impedance for the two inputs (as is commonly
done for matched input bias current devices).
The total output noise is computed in a similar fashion to
output offset voltage. Using the input noise voltage and two
input noise currents, the output noise is developed through
the same gain equations for each term but combined as the
square root of the sum of squared contributing elements.
See Application Note OA-12 for a full discussion of noise
calculations for current feedback amplifiers.
Printed Circuit Layout
As with any high speed component, a careful attention to the
board layout is necessary for optimum performance. Evalu-
ation PC boards (CLC730013-DIP, CLC730027-SOIC, and
CLC730068-SOT) for the CLC409 are available. This addi-
tional supply bypassing capacitor, C
, can easily be added
to the board if desired. Further layout suggestions can be
found in Application Note OA-15.
01274820
FIGURE 3. Input Amplifier to ADC
C
www.national.com
8
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| CLC409AMC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Very Wideband, Low Distortion Monolithic Op Amp |
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