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參數(shù)資料
| 型號： | CLC408AJE-TR |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| 中文描述： | OP-AMP, 11000 uV OFFSET-MAX, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 199K |
| 代理商： | CLC408AJE-TR |
http://www.national.com
6
Figure 3: Transimpedance Gain
DC Design (level shifting)
Figure 4 shows a DC level shifting circuit for inverting
gain configurations. V
ref
produces a DC output level shift
R
R
ref
of
which is independent of the DC output
produced by V
in
.
Figure 4: Level Shifting Circuit
DC Design (DC offsets)
The DC offset model shown in Fig. 5 is used to calculate
the output offset voltage. The equation for output offset
voltage is:
(
The current offset terms, I
BN
and I
BI
,
do not track
each other
. The specifications are stated in terms of
magnitude only. Therefore, the terms V
os
, I
BN
, and I
BI
can have either polarity. Matching the equivalent
resistance seen at both input pins does not reduce the
output offset voltage.
Figure 5: DC Offset Model
DC Design (output loading)
R
L
, R
f
, and R
g
load the op amp output. The equivalent
load seen by the output in Figure 5 is:
{
R
L(eq)
=
R
L
|| (R
f
+ R
eq2
), non-inverting gain
R
L
|| R
f
, inverting and transimpedance gain
The equivalent output load (R
L(eq)
) needs to be large
enough so that the output current can produce the
required output voltage swing.
AC Design (small signal bandwidth)
The CLC408 current-feedback amplifier bandwidth is a
function of the feedback resistor (R
f
), not of the DC voltage
gain (A
V
). The bandwidth is approximately proportional
1
R
f
to
As a rule, if R
f
doubles, the bandwidth is cut in half.
Other AC specifications will also be degraded.
Decreasing R
f
from the recommended value increases
peaking, and
for very small values of R
f
oscillation
will occur.
AC Design (minimum slew rate)
Slew rate influences the bandwidth of large signal
sinusoids. To determine an approximate value of slew
rate necessary to support a large sinusoid, use the
following equation:
SR
>
5
f
V
peak
where V
peak
is the peak output sinusoidal voltage.
The slew rate of the CLC408 in inverting gains is always
higher than in non-inverting gains.
AC Design (linear phase/constant group delay)
The recommended value of R
f
produces minimal peaking
and a reasonably linear phase response. To
improve phase linearity when |A
v
| < 6, increase R
f
approximately 50% over its recommended value. Some
adjustment of R
f
may be needed to achieve phase
linearity for your application. See the
AC Design
(small signal bandwidth)
sub-section for other effects
of changing R
f
.
Propagation delay is approximately equal to group delay.
Group delay is related to phase by this equation:
where
φ
(f) is the phase in degrees. Linear phase implies
constant group delay. The technique for achieving linear
phase also produces a constant group delay.
AC Design (peaking)
Peaking is sometimes observed with the recommended
R
f
. If a small increase in R
f
does not solve the problem,
then investigate the possible causes and remedies
listed below:
+
CLC408
-
408 Fi 3
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
CC
0.1
μ
F
6.8
μ
F
V
EE
R
t
3
2
4
8
6
+
I
in
V
in
R
g
+
CLC408
-
R
f
V
o
V
ref
R
ref
R
t
V
,
ref
f
V
V
I
R
1
R
R
I
R
o
os
BN
eq1
f
eq2
BI
f
=
+
)
+
+
(
)
R
eq1
R
f
+
CLC408
-
R
eq2
I
BI
I
BN
V
os
-
V
o
R
L
+
.
τ
φ
d
φ
gd
d
f
1
360
f
f
1
360
f
f
( )
=
°
( )
≈
°
( )
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PDF描述 |
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| CLC408AJP | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408ALC | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC409AJP | JT 16C 16#16 SKT WALL RECP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC408AJE-TR13 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJP | 制造商:Texas Instruments 功能描述: |
| CLC408ALC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC409 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Very Wideband, Low Distortion Monolithic Op Amp |
| CLC409 WAF | 制造商:Texas Instruments 功能描述: |
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