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參數(shù)資料
| 型號： | CLC408 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| 中文描述： | Comlinear CLC408高速，低功耗，線路驅(qū)動器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 199K |
| 代理商： | CLC408 |
http://www.national.com
8
Unity gain applications are limited by the Common-Mode
Input Range. At greater non-inverting gains, the Output
Voltage Range becomes the limiting factor. Inverting
gain applications are limited by the Output Voltage
Range (and by the previous amplifier’s ability to drive
R
g
). For transimpedance gain applications, the sum of
the input currents injected at the inverting input pin of
the op amp needs to be:
, where V
max
is the
Output Voltage Range (see the
DC Gain (transimpedance)
sub-section for details).
The equivalent output load needs to be large enough
so that the output current can produce the required out-
put voltage swing. See the
DC Design (output loading)
sub-section for details.
Dynamic Range (noise)
The output noise defines the lower end of the CLC408’s
useful dynamic range. Reduce the value of resistors in
the circuit to reduce noise.
See the App Note
Noise Design of CFB Op Amp
Circuits
for more details. Our SPICE models support noise
simulations.
Dynamic Range (distortion)
The distortion plots in the
Typical Performance
Characteristics
section show distortion as a function
of load resistance, frequency, and output amplitude.
Distortion places an upper limit on the CLC408’s
dynamic range.
The CLC408’s output stage combines a voltage buffer
with a complementary common emitter current source.
The interaction between the buffer and the current
source produces a small amount of crossover distortion.
This distortion mechanism dominates at low output swing
and low resistance loads. To avoid this type of distortion,
use the CLC408 at high output swing.
Realized output distortion is highly dependent upon the
external circuit. Some of the common external circuit
choices that can improve distortion are:
I
Short and equal return paths from the load to
the supplies
I
De-coupling capacitors of the correct value
I
Higher load resistance
Printed Circuit Board Layout
High frequency op amp performance is strongly dependent
on proper layout, proper resistive termination and
adequate power supply decoupling. The most important
layout points to follow are:
I
Use a ground plane
I
Bypass power supply pins with:
I
monolithic capacitors of about 0.1
μ
F place
less than 0.1” (3mm) from the pin
I
tantalum capacitors of about 6.8
μ
F for
large signal current swings or improved
power supply noise rejection;
we recommend a minimum of 2.2
μ
F
for any circuit
I
Minimize trace and lead lengths for components
between the inverting and output pins
I
Remove ground plane underneath the amplifier
package and 0.1” (3mm) from all input/output pads
I
For prototyping, use flush-mount printed circuit
board pins;
never use high profile DIP sockets
.
Evaluation Board
Separate evaluation boards are available for proto-typing
and measurements. Additional information is available in
the evaluation board literature.
SPICE Models
SPICE models provide a means to evaluate op amp
designs. Free SPICE models are available that:
I
Support Berkeley SPICE 2G and its many
derivatives
I
Reproduce typical DC, AC, Transient, and
Noise performance
I
Support room temperature simulations
The
readme
file that accompanies the models lists the
released models, and provides a list of modeled
parameters. The application note
Simulation
SPICE Models for Comlinear’s Op Amps
schematics and detailed information.
contains
The circuit shown in the
Typical Application
schematic
on the front page operates as a full duplex cable driver
which allows simultaneous transmission and reception of
signals on one transmission line. The circuit on either
side of the transmission line uses the CLC408 as a cable
driver, and the CLC426 as a receiver. V
oA
is an attenuated
version of Vi
nA
, while V
oB
is an attenuated version of V
inB
.
R
m1
is used to match the transmission line. R
f2
and R
g2
set the DC gain of the CLC426, which is used in a differ-
ence mode. R
t2
provides good CMRR and DC offset. The
CLC408 is shown in a unity gain configuration because it
consumes the least power of any gain, for a given load.
For proper operation we need R
f2
= R
g2
.
The receiver output voltages are:
where A is the attenuation of the cable, Z
o(408)
(j
ω
) is the
output impedance of the CLC408 (see the
Closed-Loop
Output Resistance
plot), and
|
Z
o(408)
(j
ω
)
|
<< R
m1
.
I
V
R
in
max
f
≤
CLC408 Applications
V
V
A
V
2
1
R
R
Z
(j )
R
outA(B)
inA(B)
inB(A)
f2
g2
o(408)
m1
≈
+
+
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC408AJE | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE-TR | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE-TR13 | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJP | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408ALC | Comlinear CLC408 High-Speed, Low-Power Line Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC408AJE | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE-TR | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE-TR13 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJP | 制造商:Texas Instruments 功能描述: |
| CLC408ALC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
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