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參數(shù)資料
| 型號(hào)： | CLC407AJE |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | IC-SM-PROG GAIN BUFFER |
| 中文描述： | BUFFER AMPLIFIER, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 328K |
| 代理商： | CLC407AJE |
Closed Loop Gain Selection
The CLC407 is a current feedback op amp with
R
f
= R
g
= 250
on chip (in the package). Select from
three closed loop gains without using any external gain or
feedback resistors. Implement gains of +2, +1, and
-1V/V by connecting pins 2 and 3 as described in the
chart below.
The gain accuracy of the CLC407 is excellent and
stable over temperature change. The internal gain
setting resistors, R
f
and R
g
are diffused silicon resistors
with a process variation of ± 20% and a temperature
coefficient of 2000ppm/°C. Although their absolute
values change with processing and temperature, their
ratio (R
f
/R
g
) remains constant. If an external resistor is
used in series with R
g
, gain accuracy over temperature
will suffer .
Non-Inverting Unity Gain Considerations (A
v
= +1V/V)
Achieve a gain of +1V/V by removing all resistive and
capacitive connections between pin 2 and ground plane.
Any capacitive coupling between pin 2 and ground will
cause high frequency peaking in the frequency domain
response and overshoot in the time domain response.
Minimize this capacitive coupling during layout by removing
ground plane near pins 1, 2, and 3. This minimization
should produce a response similar to the plot labeled
“open” in Graph 1. If desired flatness is greater than plot
“open” in Graph 1, two options remain to further flatten
the frequency response. First, try shorting the inverting
input (pin 2) to the non-inverting input (pin 3). This
response is labeled “short” in Graph 1. Next, try
inserting a 300
resistor
R
between the non-inverting
input (pin 2) as shown in Figure 1. This response is
labeled “300
” in Graph 1. Notice an “open” produces a
response with obvious peaking and maximum bandwidth,
a “short” minimizes peaking and bandwidth, and finally
300
slightly extends bandwidth with minimal peaking.
Graph 1
Gain
Acl
Input Connections
Non-Inverting (pin3)
Inverting (pin2)
-1V/V
+1V/V
+2V/V
ground
input signal
input signal
input signal
NC (open)
ground
CLC407 Typical Performance Characteristics
(A
V
= +2, R
f
= 250
: V
cc
= + 5V, R
L
= 100
unless specified)
I
BI
, I
BN
, V
IO
vs. Temperature
O
I
-60
-20
140
Temperature (
o
C)
V
IO
4.0
3.0
2.0
1.0
0
-1.0
I
B
,
B
μ
A
1.0
0
-1.0
-2.0
-3.0
-4.0
20
60
100
I
BI
I
BN
CLC407 OPERATION
Small Signal Pulse Response
O
Time (5ns/div)
0.20
0.10
-0.10
-0.20
0.00
A
V
-1
A
V
+2
Large Signal Pulse Response
O
Time (5ns/div)
2.0
1.0
-1.0
-2.0
0.0
A
V
-1
A
V
+2
Settling Time vs. Capacitive Load
S
s
(
10
100
1000
C
L
(pF)
C
L
1k
R
s
+
CLC407
-
250
250
V
o
= 2V step
T
s
R
s
50
40
30
20
10
0
R
s
)
100
80
60
40
20
0
Short Term Settling Time
V
o
Time (ns)
0.2
0.1
-0.1
-0.2
0.0
0
20
100
80
60
40
V
out
= 2Vstep
PSRR and CMRR
P
10k
100k
1M
Frequency (Hz)
10M
100M
60
50
40
30
20
10
PSRR
CMRR
Frequency Response vs.
Unity Gain Configuration
M
Frequency (MHz)
1
10
100
Short
300
Open
http://www.national.com
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC407AJP | IC-PROG GAIN BUFFER |
| CLC408 | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE-TR | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE-TR13 | Comlinear CLC408 High-Speed, Low-Power Line Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC407AJP | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:IC-PROG GAIN BUFFER |
| CLC407SMD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Buffer/Voltage Follower |
| CLC408 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE-TR | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
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