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參數(shù)資料
| 型號： | CLC407AJ |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low-Cost, Low-Power Programmable Gain Buffer with Disable |
| 中文描述： | 低成本，低功耗可編程增益緩沖器具有禁用 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 328K |
| 代理商： | CLC407AJ |
Figure 1
Enable/Disable Operation Using +5V Supplies
The CLC407 has a TTL & CMOS logic compatible
disable function. Apply a logic low (i.e. < 0.8V) to pin
8, and the CLC407 is guaranteed disabled across its
temperature range. Apply a logic high to pin 8, (i.e. >
2.0V) and the CLC407 is guaranteed enabled. Voltage,
not current, at pin 8 determines the enable/disable
state of the CLC407.
Disable the CLC407 and its inputs and output become
high impedances. While disabled, the CLC407’s quies-
cent power drops to 8mW.
Use the CLC407’s disable to create analog switches or
multiplexers. Implement a single analog switch with
one CLC407 positioned between an input and output.
Create an analog multiplexer with several CLC407s.
Tie the outputs together and put a different signal on
each CLC407 input.
Operate the CLC407 without connecting pin 8. An
internal 20k
pull-up resistor guarantees the CLC407
is enabled when pin 8 is floating.
Enable/Disable Operation for Single or
Unbalanced Supply Operation
Figure 2
Figure 2 illustrates the internal enable/disable
operation of the CLC407. When pin 8 is left floating or
is tied to +V
cc
, Q
1
is on and pulls tail current through
the CLC407 circuitry. When pin 8 is less than 0.8V
above the supply mid-point, Q
1
stops tail current from
flowing in the bias circuitry. The CLC407 is now disabled.
Disable Limitations
The internal feedback resistor, R
f
limits off isolation in
inverting gain configurations. Do not apply voltages
greater than +V
cc
or less than -V
ee
to pin 8.
Input - Bias Current, Impedances, and Source
Termination Considerations
The CLC407 has:
a 6M
non-inverting input impedance.
100nA non-inverting input bias current.
If a large source impedance application is considered,
remove all parasitic capacitance around the non-invert-
ing input and source traces. Parasitic capacitances
near the input and source act as a low-pass filter and
reduce bandwidth.
Current feedback op amps have uncorrelated input
bias currents. These uncorrelated bias currents
prevent source impedance matching on each input
from cancelling offsets. Refer to application note
OA-07 of the data book to find specific circuits to
correct DC offsets.
Layout Considerations
Whenever questions about layout arise, USE THE
EVALUATION BOARD AS A TEMPLATE.
Use the 730013 and 730026 evaluation boards for the
DIP and SOIC respectively. These board layouts were
optimized to produce the typical performance of the
CLC407 shown in the data sheet. To reduce parasitic
capacitances, the ground plane was removed near
pins 2, 3, and 6. To reduce series inductance, trace
lengths of components and nodes were minimized.
Parasitics on traces degrade performance. Minimize
coupling from traces to both power and ground
planes. Use low inductance resistors for leaded
components .
Do not use dip sockets for the CLC407 DIP amplifiers.
These sockets can peak the frequency domain
response or create overshoot in the time domain
response. Use flush-mount socket pins if socketing
cannot be avoided. The 730013 circuit board device
holes are sized for Cambion P/N 450-2598 socket pins
or their functional equivalent.
Insert the back matching resistor
R
out
shown in
Figure 3 when driving coaxial cable or a capacitive
load. Use the plot in the typical performance section
labeled “Settling Time vs. Capacitive Load” to determine
the optimum resistor value for R
out
for different capac-
itive loads. This optimal resistance improves settling
time for pulse-type applications and increases stability.
Figure 3
SMA
Output
SMA
Input
R
in
50
R
out
50
+5V
+
-5V
+
C
1
0.1
μ
fd
C
2
0.1
μ
fd
C
3
6.8
μ
fd
C
4
6.8
μ
fd
J
1
= 0
1
CLC407
7
6
8
5
3
4
2
20k
20k
Pin 8
Disable
Q
2
Q
1
Pin 4
-V
ee
20k
Bias
Circuitry
I Tail
Supply
Mid-Point
Pull-up
Resistor
Pin 7
+V
cc
CLC407
NOTE: Pins 4, 7, 8 are external
V
cc
-V
ee
2
SMA
Output
SMA
Input
R
in
50
R
out
50
R
1
CLC407
7
6
8
5
3
4
2
5
http://www.national.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC407AJE | IC-SM-PROG GAIN BUFFER |
| CLC407AJP | IC-PROG GAIN BUFFER |
| CLC408 | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE-TR | Comlinear CLC408 High-Speed, Low-Power Line Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC407AJE | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:IC-SM-PROG GAIN BUFFER |
| CLC407AJP | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:IC-PROG GAIN BUFFER |
| CLC407SMD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Buffer/Voltage Follower |
| CLC408 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Comlinear CLC408 High-Speed, Low-Power Line Driver |
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