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參數(shù)資料
| 型號： | CLC407 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low-Cost, Low-Power Programmable Gain Buffer with Disable |
| 中文描述： | 低成本，低功耗可編程增益緩沖器具有禁用 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 328K |
| 代理商： | CLC407 |
Use
operating this amplifier. Choose quality 0.1
μ
F ceramics
for C
1
and C
2
. Choose quality 6.8
μ
F tantalum capacitors
for C
3
and C
4
. Place the 0.1
μ
F capacitors within 0.1
inches from the power pins. Place the 6.8
μ
F capacitors
within 3/4 inches from the power pins.
power-supply
bypassing
capacitors
when
Special Evaluation Board
Considerations for the CLC407
To optimize off-isolation of the CLC407, cut the R
f
trace on
both the 730013 and the 730027 evaluation boards. This
cut minimizes capacitive feedthrough between the input
and the output. Figure 4 shows where to cut both evalu-
ation boards for improved off-isolation.
Figure 4
Video Performance vs. I
EX
Improve the video performance of the CLC407 by drawing
extra current from the amplifier’s output stage. Using a
single external resistor as shown in Figure 5, you can
adjust the differential phase. Video performance vs. I
EX
is
illustrated below in Graph 2. This graph represents
positive video performance with negative synchronization
pulses.
Graph 2
The value for Rpd in Figure 5 is determined by:
at +5V supplies.
Figure 5
Video Cable Driver
The CLC407 was designed to produce exceptional video
performance at all three closed-loop gains. At the non-
inverting gain of 2V/V configuration, back terminate the
cable using R
out
. A typical cable driving configuration is
shown below in Figure 6.
Figure 6
N:1 Mux Cable Driver
The CLC407 is capable of multiplexing several signals on a
single analog output bus. The front page shows how a 2:1
multiplexer is implemented. An N:1 multiplexer is implement-
ed in an analogous fashion by using an N:1 decoder to
enable/disable the appropriate number of CLC407’s.
Ordering Information
Model
Temperature Range
Description
CLC407AJP
CLC407AJE
CLC407AIB
CLC407ALC
CLC407A8B
CLC407AMC
Contact factory for other packages and DESC SMD number.
-40
C to +85
C
-40
C to +85
C
-40
C to +85
C
-40
C to +85
C
-55
C to +125
C
-55
C to +125
C
8-pin PDIP
8-pin SOIC
8-pin CerDIP
dice
8-pin CerDIP, MIL-STD-883
dice, MIL-STD-883
Package Thermal Resistance
Package
q
jc
q
jA
Plastic (AJP)
Surface Mount (AJE)
CerDip
75
/W
130
/W
65
/W
125
/W
150
/W
155
/W
730013
REV C
Cut trace here
SMA
Output
SMA
Input
R
in
50
R
out
50
I
EX
+5V
+
-5V
+
C
1
0.1
μ
fd
C
2
0.1
μ
fd
C
3
6.8
μ
fd
C
4
6.8
μ
fd
J
1
= 0
1
CLC407
7
6
8
5
3
4
2
R
pd
Differential Gain & Phase vs. I
EX
D
I
EX
in mA
405 G
h1
0.25
0.20
0.15
0.10
0.05
0
2
0
4
6
8
10
D
0.25
0.20
0.15
0.10
0.05
0
Phase
Gain
12
14
16
18
R
5
I
pd
EX
=
Coax
50
SMA
Input
R
in
50
R
out
50
+5V
+
-5V
+
C
1
0.1
μ
fd
C
2
0.1
μ
fd
C
3
6.8
μ
fd
C
4
6.8
μ
fd
J
1
= 0
1
CLC407
7
6
8
5
3
4
2
50
Video
Output
R
R
R
R
R8
R5
C
R
R
C
R
OUT
C6
C2
C1
C5
C8
IN
R
R
RF
C7
-V
cc
+V
cc
GND
A Na ti on a l Semi con du ctor C ompa n y
(303) 226-0500
+
+
407 Fig 3 (Right)
Cut trace here
http://www.national.com
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC407AJ | Low-Cost, Low-Power Programmable Gain Buffer with Disable |
| CLC407AJE | IC-SM-PROG GAIN BUFFER |
| CLC407AJP | IC-PROG GAIN BUFFER |
| CLC408 | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| CLC408AJE | Comlinear CLC408 High-Speed, Low-Power Line Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC407A8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Buffer/Voltage Follower |
| CLC407AIB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Buffer/Voltage Follower |
| CLC407AJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Cost, Low-Power Programmable Gain Buffer with Disable |
| CLC407AJE | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:IC-SM-PROG GAIN BUFFER |
| CLC407AJP | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:IC-PROG GAIN BUFFER |
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