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參數(shù)資料
| 型號(hào)： | CLC404 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Wideband, High Slew Rate, Monolithic Operational Amplifier(寬帶高轉(zhuǎn)換率單片運(yùn)算放大器) |
| 中文描述： | 寬帶，高擺率，單片運(yùn)算放大器（寬帶高轉(zhuǎn)換率單片運(yùn)算放大器） |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 275K |
| 代理商： | CLC404 |
Application Division
(Continued)
Slew Rate
Slew rate limiting is a nonlinear response which occurs in
amplifiers when the output voltage swing approaches hard,
abrupt limits in the speed at which it can change. In most
applications, this results in an easily identifiable “slew rate”
as well as a dramatic increase in distortion for large signal
levels. The CLC404 has been designed to provide enough
slew rate to avoid slew rate limiting in almost all circuit
configurations. The large signal bandwidth of 165MHz,
therefore, is nearly the same as the 175MHz small signal
bandwidth. The result is a low-distortion, linear system for
both small signals and large signals.
Slew rate and large signal performance in the CLC404 can
best be understood by first comparing the small and large
signal performance plots at a gain of +6. In the CLC404,
there is almost no difference between large and small signal
performance at this gain. Large signal performance in the
CLC404 at a gain of + is not slew rate limited. (In an amplifier
which is slew limiting, the large signal response rolloff has an
abrupt break indicating the onset of slew rate limitation.)
The CLC404 reaches slew rate limits only for low
non-inverting gains. In other words, slew rate limiting is
constrained by common mode voltage swings at the input.
(This is different from traditional slew rate constraints.) The
large-signal frequency response plot at a gain of +2 shows a
break in the response, which shows that slew rate limit has
been reached. Note also that the frequency response plots
at gain of +21 show that the large signal and small signal
responses are nearly identical.
Differential Gain and Phase
Differential gain and phase are measurements useful prima-
rily in composite video channels. Differential gain and phase
are measured by monitoring the gain and phase of a high
frequency carrier (3.56MHz for NTSC composite video) as
the output of the amplifier is swept over a range of DC
voltages. Any changes in gain and phase at the carrier
frequency are the desired measurement, differential gain
and phase.
Specifications for the CLC404 include differential gain and
phase. The test signals used are based on a 1V
pp
video
level. Test conditions used are the following.
DC sweep range: 0 to 100 IRE units (black to white)
Carrier: 3.58MHz at 40 IRE units peak to peak
The amplifier is specified for a gain of +2, and 150
load (for
a backmatched 75
system.) IRE amplitudes are referred to
75
at the load of a video system. This is a different condi-
tion from the rest of the specifications (A
V
= +6, R
i
= 100
).
Source Impedance
For best results, source impedance in the non-inverting cir-
cuit configuration (see Figure 1) should be kept below 3k
Above 3k
it is possible for oscillation to occur, depending
on other circuit parasitics. Depending on the signal source, a
resistor with a value of less than 3k
may be used to
terminate the non-inverting input to ground.
Feedback Resistor
In current-feedback op amps, the value of the feedback
resistor plays a major role in determining amplifier dynamics.
It is important to select the correct value resistor. The
CLC404 provides optimum performance with a 500
feed-
back resistor. Furthermore, the specifications shown on the
previous pages are valid only when a 500
feedback resis-
tor is used. Selection of an incorrect value can lead to severe
rolloff in frequency-response (if the resistor value is too
large) or peaking or oscillation (if the value is too low).
Printed Circuit Layout
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. In the non-inverting configura-
tion, the amplifier is sensitive to stray capacitance to ground
at the inverting input. Hence, the inverting node connections
should be small with minimal coupling to the ground plane.
Shunt capacitance across the feedback resistor should not
be used to compensate for this effect.
Parasitic or load capacitance directly on the output will intro-
duce additional phase shift in the loop degrading the loop
phase margin and leading to frequency response peaking. A
DS012746-17
FIGURE 2. Recommended Inverting Gain Circuit
C
www.national.com
8
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相關(guān)代理商/技術(shù)參數(shù) |
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| CLC404AJE | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Wideband, High-Slew Rate, Monolithic Op Amp |
| CLC404AJM5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CLC404AJM5X | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CLC404AJP | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Wideband, High-Slew Rate, Monolithic Op Amp |
| CLC404AJ-QML | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current-Feedback Operational Amplifier |
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