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參數(shù)資料
| 型號： | CLC111A8 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Ultra-High Slew Rate, Closed-Loop Buffer |
| 中文描述： | 超高壓擺率，閉環(huán)緩沖器 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 252K |
| 代理商： | CLC111A8 |
Application Division
Operation
the CLC111 is a low-power, very high speed unity gain buffer.
It uses a closed loop topology which allows for accuracy not
usually found in high speed open loop buffers. A slew
enhanced front end allows for low quiescent power while not
sacrificing AC performance.
Single Supply Operation
Although the CLC111 is specified to operate from split
±
5V
power supplies, there is no internal ground reference that
prevents operation from a single voltage power supply. For
single supply operation, the input signal should be biased at
a DC value of 1/2V
. This can be accomplished by AC
coupling and rebiasing, as shown in Figure 1
The
above
electrical
specifications
performance specifications for the CLC111 at 25 C while
operating from a single +3V or a single +5V power supply.
provide
typical
Printed Circuit Layout and Supply Bypassing
As with any high frequency device, a good PCB layout is
required for optimum performance. This is especially
important for a device as fast as the CLC111.
To minimize capacitive feedthrough, pins 2, 3, 6, and 7
should be connected to the ground plane, as shown in
Figure 1 Input and output traces should be laid out as
transmission lines with the appropriate termination resistors
very near the CLC111. On a 0.065 inch epoxy PCB material,
a 50 transmission line (commonly called stripline) can be
constructed by using a trace width of 0.01” over a complete
ground plane.
Figure 1 shows recommended power supply bypassing.
The ferrite beads are optional and are recommended only
where additional isolation is needed from high frequency
(
>
400MHz) resonances in the power supply.
Parasitic or load capacitance directly on the output of the
CLC111 will introduce additional phase shift in the device.
This phase shift can decrease phase margin and increase
frequency response peaking. A small series resistor before
the capacitance effectively decouples this effect. The graphs
in this data sheet illustrate the required resistor value and the
resulting performance vs. capacitance.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products), which have low parasitic reactances,
were used to develop the data sheet specifications.
Precision
carbon
composition
resistors
or
standard
spirally-trimmed RN55D metal file resistors will work, though
they will cause a slight degradation of AC performance due
to their reactive nature at high frequencies.
Evaluation Boards
Evaluation boards are available from National as part
numbers CLC730012 (DIP) and CLC730045 (SOIC). This
board was used in the characterization of the device and
provides optimal performance. Designers are encouraged to
copy these printed circuit board layouts for their applications.
DS012720-21
FIGURE 1. Recommended Circuit & Evaluation Board Schematic
C
www.national.com
8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC111A8B | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Ultra-High Slew Rate, Closed-Loop Buffer |
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| CLC111AJE | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Ultra High Slew Rate, Closed Loop Buffer |
| CLC111AJP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CLC111ALC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Ultra-High Slew Rate, Closed-Loop Buffer |
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