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參數(shù)資料
| 型號(hào)： | CLC109 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low-Power, Wideband, Closed-Loop Buffer |
| 中文描述： | 低功耗，寬帶，閉環(huán)緩沖器 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | CLC109 |
PARAMETERS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
CONDITIONS
V
CC
= 3V
V
CC
= 5V
UNITS
V
out
< 0.5V
pp
V
out
< 2.0V
pp
V
< 0.5V
DC to 30MHz
DC to 200MHz
DC to 60MHz
30
90
35
MHz
MHz
gain flatness
flatness
peaking
rolloff
TIME DOMAIN RESPONSE
rise and fall time
3
0
0.3
0
1.5
dB
dB
dB
0.5V step
2.0V step
0.5V step
0.5V step
13.9
4.7
13.5
0
200
ns
ns
%
V/
μ
s
overshoot
slew rate
DISTORTION AND NOISE RESPONSE
2
nd
harmonic distortion
0
35
0.5V
pp
,20MHz
1.0V
pp
,20MHz
0.5V
pp
,20MHz
1.0V
pp
,20MHz
-32
dBc
dBc
dBc
dBc
-37
3
rd
harmonic distortion
-29
-43
STATIC DC PERFORMANCE
small-signal gain
supply current
MISCELLANEOUS PERFORMANCE
output voltage range
AC-coupled
R
L
=
∞
0.89
0.75
0.94
1.6
V/V
mA
R
L
=
∞
R
L
=100
1.5
1.1
2.8
2.6
V
pp
V
pp
Electrical Characteristics
(V
CC
=+3V or V
CC
=+5V, -V
ee
= 0V, T
A
=+25°C, R
L
= 100
, unless noted)
Operation
The CLC109 is a low-power, high-speed unity-gain buffer.
It uses a closed-loop topology which allows for accuracy
not usually found in high-speed buffers. A closed-loop
design provides high accuracy and low output impedance
through a wide bandwidth.
Single Supply Operation
Although the CLC109 is specified to operate from split
±5V power supplies, there is no internal ground reference
that prevents operation from a single voltage power
supply. For single supply operation the input signal should
be biased at a DC value of
V
. This can be
accomplished by AC coupling and rebiasing as shown in
the "Typical Application" illustrations on the front page.
The above electrical specifications provide typical
performance specifications for the CLC109 at 25°C while
operating from a single +3V or a single +5V power supply.
Printed Circuit Layout and Supply Bypassing
As with any high-frequency device, a good PCB layout is
required for optimum performance. This is especially
important for a device as fast as the CLC109.
To minimize capacitive feedthrough, pins 2, 3, 6, and 7
should be connected to the ground plane, as shown in
Figure 1. Input and output traces should be laid out as
transmission lines with the appropriate termination resistors
very near the CLC109. On a 0.065 inch epoxy PCB
material, a 50
transmission line (commonly called stripline)
can be constructed by using a trace width of 0.1" over a
complete ground plane.
Figure 1 shows recommended power supply bypassing.
Parasitic or load capacitance directly on the output of the
CLC109 will introduce additional phase shift in the device.
This phase shift can decrease phase margin and increase
frequency response peaking. A small series resistor
inserted between pin 6 and the capacitance effectively
decouples this effect. The graphs on the following page
illustrate the required resistor value and the resulting
performance vs. capacitance.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products), which have low parasitic reactances,
were used to develop the data sheet specifications.
Precision carbon composition resistors or standard spirally-
trimmed RN55D metal film resistors will work, though they
may cause a slight degradation of ac performance due to
their reactive nature at high frequencies.
Evaluation Boards
Evaluation boards are available from National as part
CLC730012 (DIP) and CLC730045 (SOIC). This board
was used in the characterization of the device and provides
optimal performance. Designers are encouraged to copy
these printed circuit board layouts for their applications.
Figure 1: Recommended circuit & evaluation
board schematic
C4
C3
C2
0.01
μ
F
C1
+5V
-5V
0.01
μ
F
6.8
μ
F
6.8
μ
F
+
+
5
4
8
1
R
out
V
out
V
in
R
in
CL2367
R
is chosen for
desired output impedance.
(CLC109 R
o
= 2.8
)
R
is chosen
for desired
input impedance.
3
http://www.national.com
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