- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379893 > CLC030VEC (NATIONAL SEMICONDUCTOR CORP) SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver PDF資料下載
參數(shù)資料
| 型號： | CLC030VEC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 329K |
| 代理商： | CLC030VEC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
Device Operation
(Continued)
Ancilliary Data Functions
The CLC030 can insert
Ancilliary Data
into the serial data
stream. This ancilliary data and related control characters
are defined in the relevant SMPTE standards and may re-
side in the horizontal and vertical blanking intervals. The
data can consist of different types of message packets in-
cluding audio data. The serial ancilliary data space must be
formatted according to SMPTE 291M. The CLC030 supports
ancilliary data in the chrominance channel (C’r/C’b) only for
high-definition operation. Ancilliary data for standard defini-
tion follows the requirements of SMPTE 125M.
Figure 3 shows the sequence of clock, data and control
signals for writing ancilliary data to the port. In ancilliary data
write mode, 10-bit
Ancilliary Data
is written into the port
using bits
AD[9:0]
and routed to the ancilliary data FIFO.
From the FIFO, the ancilliary data can be written into the
ancilliary data spaces in the serial video data stream. Ancil-
liary data write mode is invoked by making the
ANC/CTRL
input high and the
RD/WR
input low. Data presented to the
port on a falling edge of
ACLK
is written into the FIFO on the
next rising edge of
ACLK
.Ancilliary data may only be written
to the FIFO when in the ancilliary data mode. Ancilliary data
cannot be read from the port.
Admission of ancilliary data to and insertion into the video
data stream from the FIFO is controlled by a system of
masking and control bits in the control registers. The details
and functions of these control registers and bits is explained
later in this datasheet.
DS200003-9
FIGURE 1. Control Data Read Timing (2 read and 1 write cycle shown)
DS200003-10
FIGURE 2. Control Data Write Timing
C
www.national.com
11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC030 | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| CLC031A | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs |
| CLC031AVEC | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs |
| CLC031 | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs |
| CLC031VEC | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC031 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs |
| CLC03-10N_-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor |
| CLC03-12N_-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor |
| CLC03-15N_-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor |
| CLC03-18N_-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor |
發(fā)布緊急采購，3分鐘左右您將得到回復。