- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379893 > CLC021AVGZ-3.3 (NATIONAL SEMICONDUCTOR CORP) SMPTE 259M Digital Video Serializer with EDH Generation and Insertion PDF資料下載
參數(shù)資料
| 型號： | CLC021AVGZ-3.3 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SMPTE 259M Digital Video Serializer with EDH Generation and Insertion |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大小： | 428K |
| 代理商： | CLC021AVGZ-3.3 |
Device Operation
(Continued)
BUILT-IN SELF-TEST (BIST)
The CLC021 has a
built-in self-test (BIST)
function. The
BIST performs a comprehensive go/no-go test of the device.
The test uses either a full-field colour bar for NTSC or a PLL
pathological for PAL as the test data pattern. Data is input
internally in the input data register, processed through the
device and tested for errors. A go/no-go indication is given at
the Test_Output.
Table 1
gives device pin functions and
Table 2
gives the test pattern codes used for this function.
The signal level at Test_Output, pin 3, indicates a pass or fail
condition.
The BIST is initiated by applying the code for the desired
BIST to D0 through D3 (D9 through D4 are 00h) and a 27
MHz clock at the P
CLK
input. Since all parallel data inputs are
equipped with an internal pull-down device, only those inputs
D0 through D3 which require a logic-1 need be pulled high.
After the Lock_Detect output goes high indicating the VCO is
locked on frequency, TPG_Enable, pin 29, is taken to a logic
high. The Lock_Detect output may be temporarily connected
to TPG_Enable to automate BIST operation. Test_Output,
pin 3, is monitored for a pass/fail indication. If no errors have
been detected, this output will go to a logic high level ap-
proximately 2 field intervals after TPG_Enable is taken high.
If errors have been detected in the internal circuitry of the
CLC021, Test_Output will remain low until the test is termi-
nated. The BIST is terminated by taking TPG _Enable to a
logic low. Continuous serial data output is available during
the test.
10136815
FIGURE 4. Power-On Reset Sequence
10136814
FIGURE 5. Power-On Reset Sequence with Manual Reset
C
www.national.com
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC021AVGZ-5.0 | SMPTE 259M Digital Video Serializer with EDH Generation and Insertion |
| CLC021 | SMPTE 259M Digital Video Serializer with EDH Generation/Insertion(SMPTE 259M數(shù)字視頻串行器帶EDH發(fā)生/插入) |
| CLC030VEC | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| CLC030 | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| CLC031A | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC021AVGZ-5.0 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| CLC021AVGZ-5.0/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| CLC02-1N0_-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor |
| CLC02-1N2_-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor |
| CLC02-1N5_-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor |
發(fā)布緊急采購，3分鐘左右您將得到回復。