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參數(shù)資料
| 型號： | CLC014AJE-TR13/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CABLE EQUALIZER ADAPT 14-SOIC |
| 標準包裝： | 2,500 |
| 應用： | 醫(yī)用型 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 14-SOICN |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
| 配用： | SD901EVK-ND - BOARD EVAL CLC014, 016, 011, 006 SD014EVK-ND - BOARD EVALUATION CLC014 |
| 其它名稱： | *CLC014AJE-TR13 *CLC014AJE-TR13/NOPB CLC014AJE-TR13 |
OBSOLETE
SNLS010E – JUNE 1998 – REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
Supply Voltage (VCC–VEE)
0.3V, +6.5V
Maximum Junction Temperature
+150°C
Storage Temperature Range
65°C to +150°C
Lead Temperature
(Soldering 4 sec.)
+260°C
ESD Rating (3)
<500V
θJA 14-Pin SOIC (D)
95°C/W
MTTF (based on limited life test data)
4.8 x 107 hours
(1)
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
(2)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3)
Human body model, 1.5 k
in series with 100 pF; based on limited test data.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage (VCC–VEE)
4.5V to 5.5V
Operating Temperature Range
40°C to +85°C
Series Input Resistance
(In Series w/DI & DI)
100
Input Coupling Capacitance
1.0
μF
AEC Capacitor (Connected
between AEC+ & AEC
)
50 pF to 1
μF
Cable Input Voltage Swing
(1)
720 to 880 mVpp
DO/DO Minimum Voltage
(2)
VCC–1.6V
(1)
These specifications assume an 800 mVpp signal at the cable input. Levels above and below 800 mV are allowable, but performance
may vary. The cable will attenuate the signal prior to entering the equalizer.
(2)
To maintain specified performance, do not reduce DO/DO below this level.
Copyright 1998–2013, Texas Instruments Incorporated
3
Product Folder Links: CLC014
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