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參數(shù)資料
| 型號： | CLA75000 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 105K |
| 代理商： | CLA75000 |
CLA70000V
3
AC CHARACTERISTICS
The performance of the CLA70000V device depends on numerous factors including:
Supply voltage
Ambient temperature, and temperature of the devices active junctions
Gate front, i.e. the logic loading on the gate outputs
Interconnection loading on the gates
Processing tolerance, i.e. the manufacturing spreads
The CLA70000 technology library contains all the performance information for each cell in the design libraries. The PDS design software suite
accesses this data, and the simulation program automatically calculates the design's performance under the selected operating conditions. Prior
to layout, estimates of the interconnection loadings are used in the simulations. After layout, track loadings are extracted from the physical design
to allow re-simulation with actual values to confirm device performance.
The effect of those factors on the propagation delays of arange of selected cells is illustrated in the tables below.
Fanout is in gate load units
Typical
propagation
Delay Ns
5 volts 25
°
C
Worst case
Propagation
Delay (ns)
3 volts 70
°
C
Fanout
Name
Cells
Description
Symbol
Fanout = 10pF
10pF
50pF
OP3
-
STANDARD OUTPUT
BUFFER
tpLH
0.73
2.58
8.83
tpLH
0.49
1.73
5.98
OP6
-
MEDIUM OUTPUT
BUFFER
tpHL
0.50
1.77
4.88
tpLH
0.33
1.16
3.29
OP12
-
LARGE OUTPUT BUFFER
tpLH
0.38
1.35
2.91
tpLH
0.25
0.90
2.04
Typical
propagation
Delay Ns
5 volts 25
°
C
Worst case
Propagation
Delay (ns)
3 volts 70
°
C
Fanout
Name
Cells
Description
Symbol
Fanout = 2
2
4
INV2
1
INVERTER DUAL DRIVE
tpLH
0.27
0.95
1.14
tpLH
0.18
0.64
0.76
NAND2
1
2-INPUT NAND GATE
tpHL
0.39
1.37
1.75
tpLH
0.30
1.07
1.41
NOR2
1
2-INPUT NOR GATE
tpLH
0.50
1.77
2.46
tpLH
0.22
0.78
1.09
DF
4
MASTER SLAVE
D-TYPE FLIP FLOP
tpHL
0.54
1.90
2.18
tpLH
0.55
1.96
2.11
Typical
propagation
Delay Ns
5 volts 25
°
C
Worst case
Propagation
Delay (ns)
3 volts 70
°
C
Fanout
Name
Cells
Description
Symbol
Fanout = 2
2
4
IBGATE
-
LARGE 2 INPUT NAND
GATE +2 INPUT NOR
tpLH
0.34
1.20
1.39
tpLH
0.27
0.97
1.14
IBDF
-
MASTER SLAVE D-TYPE
FLIP FLOP
tpHL
0.48
1.69
1.96
tpLH
0.50
1.78
1.93
IBCMOS1
-
CMOS INPUT BUFFER
WITH 2 INPUT NAND GATE
tpLH
0.60
2.15
2.28
tpLH
0.45
1.59
1.65
OUTPUT BUFFER CELLS
INTERMEDIATE BUFFER CELLS
INTERNAL CORE CELLS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLA78000 | ASIC |
| CLA80000-SERIES | ASIC |
| CLA864 | NPN-OUTPUT DC-INPUT OPTOCOUPLER |
| CLA864A | NPN-OUTPUT DC-INPUT OPTOCOUPLER |
| CLA864B | Optoelectronic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLA75000AC120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA75000AC132 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA75000AC144 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA75000AC180 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA75000GC132 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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